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create_clock -period 1.9MHz [get_ports PHI2]
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|
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create_clock -period 87.36MHz [get_ports CLK_SLOW]
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create_clock -period 49.152MHz [get_ports CLK0]
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create_clock -period 49.152MHz [get_ports CLK1]
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derive_pll_clocks
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derive_clock_uncertainty
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set_clock_groups -asynchronous \
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-group { PHI2 } \
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-group { CLK_SLOW } \
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-group { CLK0 } \
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-group { CLK1 } \
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-group { \flash_on:flash_controller_inst|flash1|onchip_flash_0|altera_onchip_flash_block|ufm_block|osc } \
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|
-group { \
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|
\pll_v3_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] \
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\pll_v3_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] \
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|
} \
|
|
-group { \
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|
\pll_v3_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] \
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|
} \
|
|
-group { \
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|
\pll_v3_inst:pll_inst|altpll_component|auto_generated|pll1|clk[3] \
|
|
}
|
|
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# IOX_RST : OUT STD_LOGIC;
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# IOX_INT : IN STD_LOGIC;
|
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# IOX_SDA : INOUT STD_LOGIC;
|
|
# IOX_SCL : INOUT STD_LOGIC
|
|
|
|
#create_clock -period 56.67MHz -name cart_clk
|
|
#set_input_delay -clock cart_clk -max 0.0 [get_ports D[*]]
|
|
#set_input_delay -clock cart_clk -min 0.0 [get_ports D[*]]
|
|
#
|
|
#set_input_delay -clock cart_clk -max 0.0 [get_ports A[*]]
|
|
#set_input_delay -clock cart_clk -min 0.0 [get_ports A[*]]
|
|
#
|
|
#set_input_delay -clock cart_clk -max 0.0 [get_ports W_N]
|
|
#set_input_delay -clock cart_clk -min 0.0 [get_ports W_N]
|
|
#
|
|
#set_input_delay -clock cart_clk -max 0.0 [get_ports CS_COMB]
|
|
#set_input_delay -clock cart_clk -min 0.0 [get_ports CS_COMB]
|
|
#
|
|
#set_input_delay -clock cart_clk -max 0.0 [get_ports PADDLE]
|
|
#set_input_delay -clock cart_clk -min 0.0 [get_ports PADDLE]
|
|
#
|
|
#set_input_delay -clock cart_clk -max 0.0 [get_ports IRQ]
|
|
#set_input_delay -clock cart_clk -min 0.0 [get_ports IRQ]
|
|
#
|
|
#set_input_delay -clock cart_clk -max 0.0 [get_ports SID]
|
|
#set_input_delay -clock cart_clk -min 0.0 [get_ports SID]
|
|
#
|
|
#set_input_delay -clock cart_clk -max 0.0 [get_ports BCLK]
|
|
#set_input_delay -clock cart_clk -min 0.0 [get_ports BCLK]
|
|
#
|
|
#set_output_delay -clock cart_clk -max 0.0 [get_ports D[*]]
|
|
#set_output_delay -clock cart_clk -min 0.0 [get_ports D[*]]
|
|
#
|
|
#set_output_delay -clock cart_clk -max 0.0 [get_ports SOD]
|
|
#set_output_delay -clock cart_clk -min 0.0 [get_ports SOD]
|
|
#
|
|
#set_output_delay -clock cart_clk -max 0.0 [get_ports ACLK]
|
|
#set_output_delay -clock cart_clk -min 0.0 [get_ports ACLK]
|
|
#
|
|
#set_output_delay -clock cart_clk -max 0.0 [get_ports BCLK]
|
|
#set_output_delay -clock cart_clk -min 0.0 [get_ports BCLK]
|
|
#
|
|
#set_output_delay -clock cart_clk -max 0.0 [get_ports AUD[*]]
|
|
#set_output_delay -clock cart_clk -min 0.0 [get_ports AUD[*]]
|
|
#
|
|
#set_output_delay -clock cart_clk -max 0.0 [get_ports IRQ]
|
|
#set_output_delay -clock cart_clk -min 0.0 [get_ports IRQ]
|
|
#
|