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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
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ENTITY simple_counter IS
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generic
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(
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COUNT_WIDTH : natural := 1
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);
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_n : IN STD_LOGIC;
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increment : in std_logic;
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load : IN STD_LOGIC;
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load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
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current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
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);
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END simple_counter;
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ARCHITECTURE vhdl OF simple_counter IS
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signal value_next : std_logic_vector(COUNT_WIDTH-1 downto 0);
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signal value_reg : std_logic_vector(COUNT_WIDTH-1 downto 0);
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BEGIN
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-- register
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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value_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
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value_reg <= value_next;
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end if;
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end process;
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-- next state
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process(increment, value_reg, load, load_value)
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begin
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value_next <= value_reg;
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if (increment = '1') then
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value_next <= std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
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end if;
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if (load = '1') then
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value_next <= load_value;
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end if;
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end process;
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-- output
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current_value <= value_reg;
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END vhdl;
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