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---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_MISC.all;
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LIBRARY work;
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ENTITY clockgen IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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PAL : IN STD_LOGIC;
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PHI2 : IN STD_LOGIC; -- enable cycle in clk domain...
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MHZ1 : OUT STD_LOGIC; -- C64 method, 1% error
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MHZ2 : OUT STD_LOGIC -- 2x C64 method, 1% error
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);
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END clockgen;
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-- C64 output
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--PAL: XL: 2*4.43361875/5, C64: 2*4.43361875/9 -> i.e. C64/XL = 5/9 -> 2x is 10/9
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--NTSC: XL: (315/88)/2, C64: 2*(315/88)/7 -> i.e. C64/XL = 4/7 -> 2x i 8/7
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ARCHITECTURE vhdl OF clockgen IS
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signal cycle_count_next : unsigned(3 downto 0);
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signal cycle_count_reg : unsigned(3 downto 0);
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signal clk_count_next : unsigned(8 downto 0);
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signal clk_count_reg : unsigned(8 downto 0);
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signal err_next : signed(13 downto 0);
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signal err_reg : signed(13 downto 0);
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signal state_next : std_logic_vector(1 downto 0);
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signal state_reg : std_logic_vector(1 downto 0);
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constant state_sync : std_logic_vector(1 downto 0) := "00";
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constant state_count : std_logic_vector(1 downto 0) := "01";
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constant state_genbegin : std_logic_vector(1 downto 0) := "10";
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constant state_gen : std_logic_vector(1 downto 0) := "11";
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signal everyother_next : std_logic;
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signal everyother_reg : std_logic;
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BEGIN
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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cycle_count_reg <= (others=>'0');
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clk_count_reg <= (others=>'0');
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err_reg <= (others=>'0');
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state_reg <= state_sync;
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everyother_reg <= '0';
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elsif (clk'event and clk='1') then
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cycle_count_reg <= cycle_count_next;
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clk_count_reg <= clk_count_next;
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err_reg <= err_next;
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state_reg <= state_next;
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everyother_reg <= everyother_next;
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end if;
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end process;
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process(clk_count_reg,cycle_count_reg,pal,phi2,state_reg,err_reg,everyother_reg)
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variable threshold : unsigned(3 downto 0);
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variable adj1 : unsigned(17 downto 0);
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variable adj : signed(13 downto 0); -- 8.6 fixed point
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variable trig : std_logic;
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variable cycle_inc : std_logic;
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variable clk_inc : std_logic;
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variable thresh_match : std_logic;
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variable multby : unsigned(8 downto 0);
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begin
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cycle_count_next <= cycle_count_reg;
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clk_count_next <= clk_count_reg;
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state_next <= state_reg;
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err_next <= err_reg;
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everyother_next <= everyother_reg;
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trig := '0';
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cycle_inc := '0';
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clk_inc := '0';
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mhz1 <= '0';
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mhz2 <= '0';
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if (pal='1') then
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multby := to_unsigned(51,9);
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else
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multby := to_unsigned(64,9);
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end if;
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adj1:= multby * clk_count_reg;
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adj:= signed(adj1(16 downto 3)) - to_signed(64,14);
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--threshold: = "0111"; ntsc
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--threshold: = "1001"; pal
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threshold(0) := '1';
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threshold(1) := not(pal);
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threshold(2) := not(pal);
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threshold(3) := pal;
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thresh_match := '0';
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if (cycle_count_reg=threshold) then
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thresh_match := '1';
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end if;
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err_next(13 downto 0) <= err_reg(13 downto 0) + to_signed(64,14);
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case state_reg is
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when state_sync =>
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if (phi2='1') then
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state_next <= state_count;
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end if;
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when state_count =>
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clk_inc := '1';
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if (phi2='1') then
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cycle_inc := '1';
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end if;
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if (thresh_match='1') then
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state_next <= state_gen;
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clk_inc := '0';
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end if;
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when state_genbegin =>
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if (phi2='1') then
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cycle_count_next <= (others=>'0');
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state_next <= state_gen;
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err_next <= -adj;
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trig := '1';
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end if;
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when state_gen =>
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-- threshold here is other size -1, which happens to match!
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if (err_reg(13) = '0') then
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err_next <= err_reg - adj;
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trig := '1';
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cycle_inc := '1';
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end if;
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if (thresh_match='1') then
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state_next <= state_genbegin;
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end if;
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when others=>
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state_next <= state_sync;
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end case;
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if (cycle_inc='1') then
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cycle_count_next <= cycle_count_reg+1;
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end if;
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if (clk_inc='1') then
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clk_count_next <= clk_count_reg + 1;
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end if;
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if (trig='1') then
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mhz2 <= '1';
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everyother_next <= not(everyother_reg);
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mhz1 <= everyother_reg;
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end if;
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end process;
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--enable_psg_div2 : entity work.syncreset_enable_divider
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-- generic map (COUNT=>29,RESETCOUNT=>6) -- 28-22
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-- port map(clk=>clk,syncreset=>'0',reset_n=>reset_n,enable_in=>'1',enable_out=>mhz2);
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--
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--enable_psg_div1 : entity work.syncreset_enable_divider
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-- generic map (COUNT=>58,RESETCOUNT=>6) -- 28-22
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-- port map(clk=>clk,syncreset=>'0',reset_n=>reset_n,enable_in=>'1',enable_out=>mhz1);
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end vhdl;
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