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---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY enable_divider IS
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generic(COUNT : natural := 1);
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ENABLE_IN : IN STD_LOGIC;
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ENABLE_OUT : OUT STD_LOGIC
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);
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END enable_divider;
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ARCHITECTURE vhdl OF enable_divider IS
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function log2c(n : integer) return integer is
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variable m,p : integer;
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begin
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m := 0;
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p := 1;
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while p<n loop
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m:=m+1;
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p:=p*2;
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end loop;
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return m;
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end log2c;
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constant WIDTH : natural := log2c(COUNT);
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signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
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signal count_next : std_logic_vector(WIDTH-1 downto 0);
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signal enabled_out_next : std_logic;
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signal enabled_out_reg : std_logic;
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BEGIN
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-- register
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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count_reg <=std_logic_vector(to_unsigned(COUNT-1,WIDTH));
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enabled_out_reg <= '0';
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elsif (clk'event and clk='1') then
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count_reg <= count_next;
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enabled_out_reg <= enabled_out_next;
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end if;
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end process;
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-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
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process(count_reg,enable_in,enabled_out_reg)
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begin
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count_next <= count_reg;
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enabled_out_next <= enabled_out_reg;
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if (enable_in = '1') then
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count_next <= std_logic_vector(unsigned(count_reg) + 1);
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enabled_out_next <= '0';
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if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
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count_next <= std_logic_vector(to_unsigned(0,WIDTH));
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enabled_out_next <= '1';
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end if;
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end if;
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end process;
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-- output
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enable_out <= enabled_out_reg and enable_in;
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END vhdl;
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