|
<?xml version="1.0" encoding="UTF-8"?>
|
|
<simPackage>
|
|
<file
|
|
path="lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v"
|
|
type="VERILOG"
|
|
library="lvds_tx" />
|
|
<file path="lvds_tx_sim/lvds_tx.vhd" type="VHDL" />
|
|
<topLevel name="lvds_tx" />
|
|
<deviceFamily name="max10" />
|
|
</simPackage>
|