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<?xml version="1.0" encoding="UTF-8"?>
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<simPackage>
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<file
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path="lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v"
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type="VERILOG"
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library="lvds_rx" />
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<file path="lvds_rx_sim/lvds_rx.vhd" type="VHDL" />
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<topLevel name="lvds_rx" />
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<deviceFamily name="max10" />
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</simPackage>
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