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repo2/atari_chips/pokeyv2/SID/wavegen.vhdl @ 1470

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---------------------------------------------------------------------------
-- (c) 2020 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------

--See: https://sourceforge.net/p/sidplay-residfp/wiki/SID%20internals/

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY SID_wavegen IS
PORT
(
CLK : IN STD_LOGIC;
RESET_N : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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CHANGING : IN STD_LOGIC;
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DELAYSAWTOOTH : IN STD_LOGIC;
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RINGMOD : IN STD_LOGIC;
RINGMOD_OSC_MSB : IN STD_LOGIC;
TEST : IN STD_LOGIC;
LFSR_ENABLE : IN STD_LOGIC;
OSC_IN : IN STD_LOGIC_VECTOR(11 downto 0);
PULSE_WIDTH_IN : IN STD_LOGIC_VECTOR(11 downto 0);

WAVESELECT_IN : IN STD_LOGIC_VECTOR(3 downto 0);

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WAVE_DATA_NEEDED : OUT STD_LOGIC;
WAVE_DATA_READY : IN STD_LOGIC;
WAVE_DATA : IN STD_LOGIC_VECTOR(11 downto 0);

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WAVE_OUT : OUT STD_LOGIC_VECTOR(11 downto 0)
);
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END SID_wavegen;

ARCHITECTURE vhdl OF SID_wavegen IS
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signal wave_reg : std_logic_vector(11 downto 0);
signal wave_next : std_logic_vector(11 downto 0);
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signal wave0count1_reg : unsigned(9 downto 0);
signal wave0count1_next : unsigned(9 downto 0);
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signal lfsr_reg : std_logic_vector(22 downto 0);
signal lfsr_next : std_logic_vector(22 downto 0);
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signal wave_data_needed_reg : std_logic;
signal wave_data_needed_next : std_logic;
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signal pulse_comparator_reg : std_logic;
signal pulse_comparator_next : std_logic;
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signal multiple_wave_bits : std_logic;
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signal no_wave_bits : std_logic;
signal osc_del_reg : std_logic_vector(11 downto 0);
signal osc_del_next : std_logic_vector(11 downto 0);
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BEGIN
-- register
process(clk, reset_n)
begin
if (reset_n = '0') then
wave_reg <= (others=>'0');
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wave0count1_reg <= (others=>'0');
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lfsr_reg <= (others=>'1');
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pulse_comparator_reg <= '0';
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wave_data_needed_reg <= '0';
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osc_del_reg <= (others=>'0');
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elsif (clk'event and clk='1') then
wave_reg <= wave_next;
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wave0count1_reg <= wave0count1_next;
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lfsr_reg <= lfsr_next;
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pulse_comparator_reg <= pulse_comparator_next;
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wave_data_needed_reg <= wave_data_needed_next;
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osc_del_reg <= osc_del_next;
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end if;
end process;

-- next state - lfsr
--23 bit lfsr, bit0=bit22 xor bit17
-- if noise and anything else then lfsr feedback is 0, test bit can refill it
--outputs: 20, 18, 14, 11, 9, 5, 2 and 0
--updated on bit 19 0->1 transition
--ref(decap):https://sourceforge.net/p/sidplay-residfp/wiki/SID%20internals%20-%20Noise%20Generator/
process(lfsr_reg,lfsr_enable,waveselect_in,test)
variable noise_and_others : std_logic;
begin
lfsr_next <= lfsr_reg;
if (lfsr_enable='1') then
noise_and_others := or_reduce(waveselect_in(2 downto 0)) and waveselect_in(3);

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lfsr_next(0) <= (test or (lfsr_reg(22) xor lfsr_reg(17))) and not(noise_and_others);
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lfsr_next(22 downto 1) <= lfsr_reg(21 downto 0);
end if;
end process;

-- next state - wave
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process(no_wave_bits,multiple_wave_bits,wave_reg,osc_in,waveselect_in,pulse_width_in,lfsr_reg,test,ringmod,ringmod_osc_msb,pulse_comparator_reg,wave_data,wave_data_ready,enable,osc_del_reg,delaysawtooth,wave0count1_reg)
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variable noise : std_logic_vector(11 downto 0);
variable pulse : std_logic_vector(11 downto 0);
variable triangle : std_logic_vector(11 downto 0);
variable sawtooth : std_logic_vector(11 downto 0);

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variable pulse_comparator : std_logic;
variable triangle_xor : std_logic;
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variable triangle_xor_ext : std_logic_vector(10 downto 0);
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variable osc_xored : std_logic_vector(10 downto 0);
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variable osc_sawtooth : std_logic_vector(11 downto 0);

variable wave0tmp : unsigned(12 downto 0);
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begin
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wave_next <= wave_reg;
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wave0count1_next <= wave0count1_reg;
osc_del_next <= osc_del_reg;
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if (enable='1') then
osc_del_next <= osc_in;
end if;

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noise:= (others=>'0');
pulse:= (others=>'0');
triangle:= (others=>'0');
sawtooth:= (others=>'0');
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if (waveselect_in(3)='1') then
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noise(11 downto 4):= lfsr_reg(20)&lfsr_reg(18)&lfsr_reg(14)&lfsr_reg(11)&lfsr_reg(9)&lfsr_reg(5)&lfsr_reg(2)&lfsr_reg(0);
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noise(3 downto 0):= (others=>'0');
end if;

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-- direct...
-- rise: perfect, fall: 1 cycle ahead
--pulse_comparator_next <= '0';
--if (unsigned(osc_in)>unsigned(pulse_width_in)) then
-- pulse_comparator_next <= '1';
--end if;
--pulse := (others=>(pulse_comparator_next or test));

pulse_comparator_next <= '1';
if (unsigned(osc_in)<=unsigned(pulse_width_in)) then
pulse_comparator_next <= pulse_comparator_reg and not(enable);
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end if;
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if (waveselect_in(2)='1') then
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pulse := (others=>(pulse_comparator_reg or test));
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end if;

--ref: https://sourceforge.net/p/sidplay-residfp/wiki/SID%20internals%20-%20Triangle%20Waveform/
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if (delaysawtooth='1') then
osc_sawtooth:= osc_del_reg;
else
osc_sawtooth := osc_in;
end if;

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triangle_xor := not(waveselect_in(1)) and -- sawtooth on->disable invert
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((not(ringmod) and osc_sawtooth(11)) or -- not ringmod ->msb makes it invert
(ringmod and (osc_sawtooth(11) xnor ringmod_osc_msb))); -- ringmod -> both 0 or 1 -> invert
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triangle_xor_ext := (others=>triangle_xor);
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osc_xored:= osc_sawtooth(10 downto 0) xor triangle_xor_ext;
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if (waveselect_in(1)='1') then
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sawtooth := osc_sawtooth(11) & osc_xored(10 downto 0);
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end if;

if (waveselect_in(0)='1') then
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triangle(11 downto 1) := osc_xored(10 downto 0);
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triangle(0) := '0';
end if;

-- AND is what the datasheet says, but it is WRONG!
-- In fact transistors drive against each other with different resistances and
-- a corrupt waveform is generated.
-- TODO: Either compute or use flash storage (optionally)
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if (no_wave_bits='1') then
if (enable='1') then
wave0count1_next <= unsigned("0"&wave0count1_reg(8 downto 0)) + 1;
if (wave0count1_reg(9)='1') then -- carry
wave0tmp := unsigned("0"&wave_reg) - 1; -- head to zero over 2 seconds!
if (wave0tmp(12) = '1') then
wave_next <= (others=>'0');
else
wave_next <= std_logic_vector(wave0tmp(11 downto 0));
end if;
end if;
end if;
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else
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if (multiple_wave_bits='0') then
wave_next <= noise or pulse or sawtooth or triangle;
else
if (wave_data_ready='1') then
if (waveselect_in(2)='1') then
wave_next <= wave_data and pulse;
else
wave_next <= wave_data;
end if;
end if;
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end if;
end if;
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end process;

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multiple_wave_bits <= --NPST (?ST) or PS or PT
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not(waveselect_in(3)) and
(
(waveselect_in(0) and waveselect_in(1))
or
(waveselect_in(2) and (waveselect_in(0) or waveselect_in(1)))
)
;
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no_wave_bits <= not(or_reduce(waveselect_in));
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wave_data_needed_next <= (wave_data_needed_reg or (multiple_wave_bits and changing)) and not(wave_data_ready);

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--output
wave_out <= wave_reg;
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wave_data_needed <= wave_data_needed_reg;
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END vhdl;