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---------------------------------------------------------------------------
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-- (c) 2018 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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LIBRARY work;
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ENTITY gtiamax IS
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PORT
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(
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PHI2 : IN STD_LOGIC;
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CLK_OUT : OUT STD_LOGIC; -- Use PHI2 and internal oscillator to create a clock, feed out here
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CLK_SLOW : IN STD_LOGIC; -- ... and back in here, then to pll!
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D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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W_N : IN STD_LOGIC;
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CS_N : IN STD_LOGIC;
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S : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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T : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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HALT_N : IN STD_LOGIC;
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OSC : IN STD_LOGIC; -- 2x PHI0 ish, iffy duty cycle at TTL levels (at 4V its ok!)
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FO0 : OUT STD_LOGIC; -- as OSC, but corrected duty cycle
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PAL : IN STD_LOGIC; -- PAL clock (5/4...)
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GPIO : INOUT STD_LOGIC_VECTOR(11 DOWNTO 0);
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NC : IN STD_LOGIC_VECTOR(6 DOWNTO 1);
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CAD3 : IN STD_LOGIC;
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CSYNC : OUT STD_LOGIC;
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COLOR : OUT STD_LOGIC;
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LUM : OUT STD_LOGIC_VECTOR(3 downto 0)
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);
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END gtiamax;
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ARCHITECTURE vhdl OF gtiamax IS
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component int_osc is
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port (
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clkout : out std_logic; -- clkout.clk
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oscena : in std_logic := '0' -- oscena.oscena
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);
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end component;
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component pll
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port (
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inclk0 : in std_logic := '0';
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c0 : out std_logic;
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c1 : out std_logic;
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locked : out std_logic
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);
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end component;
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component osc_in is
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port (
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inclock : in std_logic := '0';
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dout : out std_logic_vector(1 downto 0);
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pad_in : in std_logic_vector(0 downto 0) := (others => '0')
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);
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end component osc_in;
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component osc_out is
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port (
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outclock : in std_logic := '0';
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din : in std_logic_vector(1 downto 0) := (others => '0');
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pad_out : out std_logic_vector(0 downto 0)
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);
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end component osc_out;
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signal OSC_CLK : std_logic;
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signal PHI2_6X : std_logic;
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signal CLK : std_logic;
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signal FAST_CLK : std_logic;
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signal RESET_N : std_logic;
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signal ENABLE_CYCLE : std_logic;
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signal DATA_CYCLE : std_logic;
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signal ADDR_IN : std_logic_vector(4 downto 0);
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signal WRITE_DATA : std_logic_vector(7 downto 0);
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signal BUS_DATA : std_logic_vector(7 downto 0);
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signal BUS_OE : std_logic;
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signal REQUEST : std_logic;
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signal WRITE_N : std_logic;
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signal GTIA_DO : std_logic_vector(7 downto 0);
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signal GTIA_WRITE_ENABLE : std_logic;
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signal PAL_CLEAN : std_logic;
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signal PAL_NTSC_N : std_logic;
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signal COLOUR_OSC : std_logic_vector(1 downto 0);
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signal COLOUR_OSC_PHASED : std_logic_vector(1 downto 0);
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signal OSC_CLEAN : std_logic;
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signal OSC_CLEAN_FAST : std_logic;
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signal OSC_CLEAN_VIDEO : std_logic;
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signal OSC_CLEAN_EVENT : std_logic;
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signal OSC_CLEAN_FAST_EVENT : std_logic;
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signal CC_FALLING_FAST : std_logic;
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signal CC_FALLING : std_logic;
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signal OSC_CLEAN_PREV_REG : std_logic;
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signal S_OUT : std_logic_vector(3 downto 0);
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signal VIDEO_COLOUR : std_logic_vector(7 downto 0);
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signal VIDEO_HSYNC : std_logic;
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signal VIDEO_VSYNC : std_logic;
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signal VIDEO_CSYNC : std_logic;
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signal VIDEO_BLANK : std_logic;
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signal VIDEO_BURST : std_logic;
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signal VIDEO_START_OF_FIELD : std_logic;
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signal VIDEO_ODD_LINE : std_logic;
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signal HALT_N_ADJ : std_logic;
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signal AN_DEL_NEXT : std_logic_vector(2 downto 0);
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signal AN_DEL_REG : std_logic_vector(2 downto 0);
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signal AN_DEL2_NEXT : std_logic_vector(2 downto 0);
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signal AN_DEL2_REG : std_logic_vector(2 downto 0);
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signal ddr_pal : std_logic_vector(1 downto 0);
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BEGIN
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--NC <= (others=>'Z');
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GPIO <= (others=>'Z');
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pal_in : osc_in
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port map
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(
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inclock => fast_clk,
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dout => colour_osc,
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pad_in(0) => pal
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);
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--colour_osc <= pal_clean when pal_ntsc_n='1' else osc_clean_video;
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col_out : osc_out
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port map
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(
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outclock => fast_clk,
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din => colour_osc_phased,
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pad_out(0)=> color
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);
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--COLOR <= colour_osc_phased;
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oscillator : int_osc
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port map
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(
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clkout => OSC_CLK,
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oscena => '1'
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);
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--phi_multiplier : entity work.phi_mult
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--port map
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--(
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-- clkin => OSC_CLK,
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-- phi2 => PHI2,
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-- clkout => PHI2_6X -- 6x phi2, aligned!
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--);
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PHI2_6X <= OSC_CLK;
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pll_inst : pll
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PORT MAP(inclk0 => CLK_SLOW,
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c0 => CLK, -- 56MHz
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c1 => FAST_CLK, -- 300MHz
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locked => RESET_N);
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process(cc_falling_fast,reset_n)
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begin
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if (reset_n='0') then
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AN_DEL_REG <= (others=>'0');
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AN_DEL2_REG <= (others=>'0');
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elsif (cc_falling_fast'event and cc_falling_fast='1') then
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AN_DEL_REG <= AN_DEL_NEXT;
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AN_DEL2_REG <= AN_DEL2_NEXT;
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end if;
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end process;
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AN_DEL_NEXT <= AN;
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AN_DEL2_NEXT <= AN_DEL_REG;
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bus_adapt : entity work.slave_timing_6502
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PORT MAP
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(
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CLK => CLK,
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RESET_N => RESET_N,
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-- input from the cart port
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PHI2 => PHI2,
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bus_addr => A,
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bus_data => D,
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-- output to the cart port
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bus_data_out => BUS_DATA,
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bus_drive => BUS_OE,
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bus_cs => NOT(CS_N),
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bus_rw_n => W_N,
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-- request for a memory bus cycle (read or write)
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BUS_REQUEST => REQUEST,
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ADDR_IN => ADDR_IN,
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DATA_IN => WRITE_DATA,
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RW_N => WRITE_N,
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-- end of cycle
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ENABLE_CYCLE => ENABLE_CYCLE,
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DATA_CYCLE => DATA_CYCLE,
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HALT_N => HALT_N,
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HALT_N_OUT => HALT_N_ADJ,
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DATA_OUT => GTIA_DO
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);
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osc_cleaner3 : entity work.correct_duty
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PORT MAP(
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CLK => FAST_CLK,
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RESET_N => RESET_N,
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CLKIN => OSC,
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CLKOUT => OSC_CLEAN_VIDEO,
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CLKOUT_EVENT => open
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);
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osc_cleaner2 : entity work.correct_duty
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PORT MAP(
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CLK => FAST_CLK,
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RESET_N => RESET_N,
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CLKIN => PAL,
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CLKOUT => PAL_CLEAN,
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CLKOUT_EVENT => open
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);
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osc_cleaner : entity work.correct_duty
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PORT MAP(
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CLK => FAST_CLK,
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RESET_N => RESET_N,
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CLKIN => OSC,
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CLKOUT => OSC_CLEAN_FAST,
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CLKOUT_EVENT => OSC_CLEAN_FAST_EVENT
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);
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CC_FALLING_FAST <= OSC_CLEAN_FAST_EVENT and not(OSC_CLEAN_FAST);
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sync_clk : entity work.synchronizer
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port map
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(
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CLK => CLK,
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RAW => OSC_CLEAN_FAST,
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SYNC => OSC_CLEAN
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);
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process(clk,reset_n)
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begin
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if (reset_n='0') then
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OSC_CLEAN_PREV_REG <= '0';
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elsif (clk'event and clk='1') then
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OSC_CLEAN_PREV_REG <= OSC_CLEAN;
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end if;
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end process;
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OSC_CLEAN_EVENT <= OSC_CLEAN_PREV_REG xor OSC_CLEAN;
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CC_FALLING <= OSC_CLEAN_EVENT and not(OSC_CLEAN);
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pal_ntsc_n <= '1'; -- TODO GPIO
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gtia1 : entity work.gtia
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PORT MAP(CLK => CLK,
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ENABLE_179 => ENABLE_CYCLE,
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WR_EN => GTIA_WRITE_ENABLE,
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RESET_N => RESET_N,
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ADDR => ADDR_IN(4 DOWNTO 0),
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CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
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DATA_OUT => GTIA_DO,
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-- pmg dma
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MEMORY_DATA_IN => D,
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ANTIC_FETCH => not(HALT_N_ADJ),
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CPU_ENABLE_ORIGINAL => DATA_CYCLE,
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PAL => pal_ntsc_n,
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-- ANTIC interface
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COLOUR_CLOCK_ORIGINAL => CC_FALLING,
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COLOUR_CLOCK => CC_FALLING,
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COLOUR_CLOCK_HIGHRES => OSC_CLEAN_EVENT,
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AN => AN_DEL2_REG,
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-- keyboard interface
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CONSOL_IN => NOT(S),
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CONSOL_OUT => S_OUT,
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-- keyboard interface
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TRIG => T,
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-- TO scandoubler...
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COLOUR_out => VIDEO_COLOUR,
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VSYNC => VIDEO_VSYNC,
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HSYNC => VIDEO_HSYNC,
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CSYNC => VIDEO_CSYNC,
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BLANK => VIDEO_BLANK,
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BURST => VIDEO_BURST,
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START_OF_FIELD => VIDEO_START_OF_FIELD,
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ODD_LINE => VIDEO_ODD_LINE
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);
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GTIA_WRITE_ENABLE <= NOT(WRITE_N) and REQUEST;
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col_phase : entity work.hue
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PORT MAP
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(
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clk => fast_clk,
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reset_n => reset_n,
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hue => video_colour(7 downto 4),
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burst => video_burst,
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blank => video_blank,
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vpos_lsb => video_odd_line,
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pal => pal_ntsc_n,
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colour_osc => colour_osc,
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colour_osc_phased => colour_osc_phased
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);
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-- Wire up pins
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CLK_OUT <= PHI2_6X;
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D <= BUS_DATA when BUS_OE='1' else (others=>'Z');
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S(0) <= '0' when S_OUT(0)='1' else 'Z';
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S(1) <= '0' when S_OUT(1)='1' else 'Z';
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S(2) <= '0' when S_OUT(2)='1' else 'Z';
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S(3) <= '0' when S_OUT(3)='1' else 'Z';
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CSYNC <= NOT(VIDEO_CSYNC);
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--COLOR <= colour_osc_phased;
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LUM(3 downto 0) <= VIDEO_COLOUR(3 downto 0);
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FO0 <= OSC_CLEAN_FAST;
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END vhdl;
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