repo2/atari_chips/pokeyv2/sigmadelta_dither.vhd @ 1527
| 1526 | markw | ---------------------------------------------------------------------------
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-- (c) 2020 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use IEEE.STD_LOGIC_MISC.all;
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ENTITY sigmadelta_dither IS
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GENERIC (
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LFSR_SEED : unsigned(15 downto 0) := x"ACE1"
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);
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC := '1';
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DITHER_OUT1 : OUT STD_LOGIC_VECTOR(15 downto 0);
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DITHER_OUT2 : OUT STD_LOGIC_VECTOR(15 downto 0);
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DITHER_OUT3 : OUT STD_LOGIC_VECTOR(15 downto 0);
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DITHER_OUT4 : OUT STD_LOGIC_VECTOR(15 downto 0)
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);
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END sigmadelta_dither;
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architecture vhdl of sigmadelta_dither is
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signal lfsr_next : unsigned(15 downto 0);
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signal lfsr_reg : unsigned(15 downto 0);
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begin
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process(CLK, RESET_N)
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begin
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if RESET_N = '0' then
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lfsr_reg <= LFSR_SEED;
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elsif rising_edge(CLK) then
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if ENABLE = '1' then
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lfsr_reg <= lfsr_next;
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end if;
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end if;
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end process;
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-- 16-bit Galois LFSR taps: 16,14,13,11
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lfsr_next <= lfsr_reg(14 downto 0) & (lfsr_reg(15) xor lfsr_reg(13) xor lfsr_reg(12) xor lfsr_reg(10));
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DITHER_OUT1 <= std_logic_vector(lfsr_reg);
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DITHER_OUT2 <= std_logic_vector(lfsr_reg(10 downto 0) & lfsr_reg(15 downto 11));
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DITHER_OUT3 <= std_logic_vector(lfsr_reg(5 downto 0) & lfsr_reg(15 downto 6));
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DITHER_OUT4 <= std_logic_vector(lfsr_reg(12 downto 0) & lfsr_reg(15 downto 13));
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end vhdl;
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