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---------------------------------------------------------------------------
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-- (c) 2026 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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--
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-- v2: indexed bank/group selection, avoiding large selected-OR reductions.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY m9k_grouped IS
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GENERIC
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(
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-- 64K configuration:
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-- (7*8 + 7)*1024 = 63 KiB in 56 M9Ks using the 9th bit
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-- +1 KiB in one extra M9K
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NUM_GROUPS : natural := 7;
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EXTRA_RAM_BLOCKS : natural := 1
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-- 48K configuration:
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-- NUM_GROUPS : natural := 5;
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-- EXTRA_RAM_BLOCKS : natural := 3
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);
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PORT
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(
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clock : IN std_logic;
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reset_n : IN std_logic := '1';
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data : IN std_logic_vector(7 DOWNTO 0);
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address : IN std_logic_vector(15 DOWNTO 0);
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we : IN std_logic;
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q : OUT std_logic_vector(7 DOWNTO 0)
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);
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END m9k_grouped;
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ARCHITECTURE rtl OF m9k_grouped IS
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constant ADDR_BITS : natural := 16;
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constant RAM_ADDR_BITS : natural := 10; -- 1 KiB per RAM block
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constant PAGE_BITS : natural := ADDR_BITS - RAM_ADDR_BITS; -- 6
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constant BYTE_BITS : natural := 8;
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constant WIDE_BIT : natural := 8;
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constant NORMAL_RAM_BLOCKS : natural := NUM_GROUPS * BYTE_BITS;
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constant GROUP_RAM_PAGES : natural := NORMAL_RAM_BLOCKS + NUM_GROUPS;
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constant TOTAL_RAM_BLOCKS : natural := NORMAL_RAM_BLOCKS + EXTRA_RAM_BLOCKS;
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constant TOTAL_MAPPED_PAGES: natural := GROUP_RAM_PAGES + EXTRA_RAM_BLOCKS;
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TYPE ram_data_t IS ARRAY(0 TO TOTAL_RAM_BLOCKS-1) OF std_logic_vector(8 DOWNTO 0);
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SIGNAL q_ram_wide : ram_data_t;
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SIGNAL write_data_ram_wide : ram_data_t;
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SIGNAL sel_ram : std_logic_vector(0 TO TOTAL_RAM_BLOCKS-1);
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SIGNAL wide_ram : std_logic;
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SIGNAL we_ram : std_logic;
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SIGNAL address_ram : std_logic_vector(RAM_ADDR_BITS-1 DOWNTO 0);
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SIGNAL address_used : std_logic_vector(ADDR_BITS-1 DOWNTO 0);
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SIGNAL state_next : std_logic_vector(0 DOWNTO 0);
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SIGNAL state_reg : std_logic_vector(0 DOWNTO 0);
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constant state_idle : std_logic_vector(0 DOWNTO 0) := "0";
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constant state_write : std_logic_vector(0 DOWNTO 0) := "1";
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SIGNAL data_next : std_logic_vector(7 DOWNTO 0);
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SIGNAL data_reg : std_logic_vector(7 DOWNTO 0);
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SIGNAL address_next : std_logic_vector(ADDR_BITS-1 DOWNTO 0);
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SIGNAL address_reg : std_logic_vector(ADDR_BITS-1 DOWNTO 0);
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BEGIN
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-- During idle/read, the RAMs see the live bus address.
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-- During the write cycle, they see the latched write address.
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address_used <= address_reg WHEN state_reg = state_write ELSE address;
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address_ram <= address_used(RAM_ADDR_BITS-1 DOWNTO 0);
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PROCESS(clock, reset_n)
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BEGIN
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IF reset_n = '0' THEN
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state_reg <= state_idle;
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data_reg <= (others => '0');
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address_reg <= (others => '0');
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ELSIF rising_edge(clock) THEN
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state_reg <= state_next;
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data_reg <= data_next;
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address_reg <= address_next;
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END IF;
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END PROCESS;
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-- Latch write address/data for one-cycle read-modify-write.
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PROCESS(state_reg, we, data, address, data_reg, address_reg)
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BEGIN
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state_next <= state_reg;
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data_next <= data_reg;
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address_next <= address_reg;
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we_ram <= '0';
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CASE state_reg IS
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WHEN state_idle =>
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IF we = '1' THEN
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data_next <= data;
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address_next <= address;
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state_next <= state_write;
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END IF;
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WHEN state_write =>
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we_ram <= '1';
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state_next <= state_idle;
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WHEN others =>
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state_next <= state_idle;
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END CASE;
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END PROCESS;
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m9k_loop: FOR i IN 0 TO TOTAL_RAM_BLOCKS-1 GENERATE
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sample_ram_inst : ENTITY work.generic_ram_infer
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GENERIC MAP
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(
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ADDRESS_WIDTH => RAM_ADDR_BITS,
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SPACE => 1024,
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DATA_WIDTH => 9
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)
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PORT MAP
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(
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clock => clock,
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reset_n => reset_n,
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data => write_data_ram_wide(i),
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address => address_ram,
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we => sel_ram(i) AND we_ram,
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q => q_ram_wide(i)
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);
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END GENERATE m9k_loop;
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-- Decode only the write-enable selection and the mode.
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-- Reads use direct indexed muxes rather than sel_ram-masked OR reductions.
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PROCESS(address_used)
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VARIABLE page : natural RANGE 0 TO 2**PAGE_BITS-1;
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VARIABLE wide_group : natural RANGE 0 TO BYTE_BITS-1;
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VARIABLE extra : natural RANGE 0 TO EXTRA_RAM_BLOCKS;
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BEGIN
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page := to_integer(unsigned(address_used(ADDR_BITS-1 DOWNTO RAM_ADDR_BITS)));
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wide_group := to_integer(unsigned(address_used(12 DOWNTO 10)));
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wide_ram <= '0';
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sel_ram <= (others => '0');
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-- 64 KiB example:
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-- pages 0..55 : normal 8-bit access to RAM blocks 0..55
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-- pages 56..62 : wide access using bit 8 of RAM blocks 0..55
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-- page 63 : normal 8-bit access to RAM block 56
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IF page < NORMAL_RAM_BLOCKS THEN
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sel_ram(page) <= '1';
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ELSIF page < GROUP_RAM_PAGES THEN
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wide_ram <= '1';
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IF wide_group < NUM_GROUPS THEN
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FOR bt IN 0 TO BYTE_BITS-1 LOOP
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sel_ram((wide_group * BYTE_BITS) + bt) <= '1';
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END LOOP;
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END IF;
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ELSIF page < TOTAL_MAPPED_PAGES THEN
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extra := page - GROUP_RAM_PAGES;
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sel_ram(NORMAL_RAM_BLOCKS + extra) <= '1';
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END IF;
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END PROCESS;
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-- RAM write data.
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-- Only the selected RAMs are written, so unselected RAM data inputs are don't-care.
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-- The assignments below avoid copying every full RAM word back to its input.
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write_data_loop: FOR i IN 0 TO TOTAL_RAM_BLOCKS-1 GENERATE
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PROCESS(wide_ram, address_used, data_reg, q_ram_wide)
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VARIABLE wide_group : natural RANGE 0 TO BYTE_BITS-1;
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BEGIN
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wide_group := to_integer(unsigned(address_used(12 DOWNTO 10)));
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write_data_ram_wide(i) <= (others => '0');
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IF wide_ram = '0' THEN
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-- Normal byte write: replace bits 0..7, preserve the packed wide bit.
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write_data_ram_wide(i)(BYTE_BITS-1 DOWNTO 0) <= data_reg;
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write_data_ram_wide(i)(WIDE_BIT) <= q_ram_wide(i)(WIDE_BIT);
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ELSE
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-- Wide write: selected group of 8 RAMs stores one bit each in bit 8.
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-- Preserve the normal byte only for RAMs in the selected group.
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IF i < NORMAL_RAM_BLOCKS THEN
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IF wide_group = (i / BYTE_BITS) THEN
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write_data_ram_wide(i)(BYTE_BITS-1 DOWNTO 0) <= q_ram_wide(i)(BYTE_BITS-1 DOWNTO 0);
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write_data_ram_wide(i)(WIDE_BIT) <= data_reg(i MOD BYTE_BITS);
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END GENERATE write_data_loop;
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-- Read mux. This replaces the previous 57-way selected OR-reduction fabric.
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PROCESS(address_used, q_ram_wide)
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VARIABLE page : natural RANGE 0 TO 2**PAGE_BITS-1;
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VARIABLE wide_group : natural RANGE 0 TO BYTE_BITS-1;
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VARIABLE extra : natural RANGE 0 TO EXTRA_RAM_BLOCKS;
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BEGIN
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page := to_integer(unsigned(address_used(ADDR_BITS-1 DOWNTO RAM_ADDR_BITS)));
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wide_group := to_integer(unsigned(address_used(12 DOWNTO 10)));
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q <= (others => '0');
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IF page < NORMAL_RAM_BLOCKS THEN
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q <= q_ram_wide(page)(BYTE_BITS-1 DOWNTO 0);
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ELSIF page < GROUP_RAM_PAGES THEN
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IF wide_group < NUM_GROUPS THEN
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FOR bt IN 0 TO BYTE_BITS-1 LOOP
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q(bt) <= q_ram_wide((wide_group * BYTE_BITS) + bt)(WIDE_BIT);
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END LOOP;
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END IF;
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ELSIF page < TOTAL_MAPPED_PAGES THEN
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extra := page - GROUP_RAM_PAGES;
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q <= q_ram_wide(NORMAL_RAM_BLOCKS + extra)(BYTE_BITS-1 DOWNTO 0);
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END IF;
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END PROCESS;
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END rtl;
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