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Revision 1554

Added by markw about 3 hours ago

Allow recording 4 selected channels at once. Gate record behind a flag. Include board version in version string instead of useless leading 1

View differences:

atari_chips/pokeyv2/build.sh
#Added like this to the generated qsf
#set_parameter -name TV 1
my $version = "131";
my $version = "31";
my %variants =
(
......
{
die "Unknown type";
}
my $board_version = $board;
$board_version =~ s/v//;
$board_version = sprintf("%02d",int($board_version*10));
my $versioncode = "${version}M$fpgasize$code1$code2";
my $versioncode = "${version}${board_version}$fpgasize$code1$code2";
$spec->{"version"} = $versioncode;
my $bus = "";
......
`echo set_global_assignment -name DEVICE $fpga >> $type.qsf`;
my $board_version = $board;
$board_version =~ s/v//;
$board_version = int($board_version*10);
`echo 'set_parameter -name board $board_version' >> $type.qsf`;
foreach my $key (sort keys %$spec)
{
my $val = $spec->{$key};
atari_chips/pokeyv2/pokeymax.vhd
enable_spdif: integer := 0;
enable_ps2: integer := 0;
enable_adc: integer := 0;
enable_routing: integer := 0;
paddle_lvds: integer := 0;
paddle_comp: integer := 1;
enable_iox: integer := 1;
......
ext_clk_enable : integer := 0; -- Use PADDLE(6) for sid clk enable, PADDLE(7) for psg
version : STRING := "DEVELOPR"; -- 8 char string atascii
board : integer := 00 -- $MAJOR$MINOR
version : STRING := "DEVELOPR" -- 8 char string atascii
);
PORT
(
......
signal GTIA_ENABLE_REG : std_logic_vector(3 downto 0);
signal ADC_VOLUME_REG : std_logic_vector(1 downto 0);
signal SIO_DATA_VOLUME_REG : std_logic_vector(1 downto 0);
signal VERSION_LOC_REG : std_logic_vector(3 downto 0);
signal VERSION_LOC_REG : std_logic_vector(2 downto 0);
signal PAL_REG : std_logic;
signal DETECT_RIGHT_NEXT : std_logic;
......
signal GTIA_ENABLE_NEXT : std_logic_vector(3 downto 0);
signal ADC_VOLUME_NEXT : std_logic_vector(1 downto 0);
signal SIO_DATA_VOLUME_NEXT : std_logic_vector(1 downto 0);
signal VERSION_LOC_NEXT : std_logic_vector(3 downto 0);
signal VERSION_LOC_NEXT : std_logic_vector(2 downto 0);
signal PAL_NEXT : std_logic;
--config infra
......
-- SAMPLE/COVOX
signal SAMPLE_AUDIO_SIGNED : SIGNED_AUDIO_TYPE(1 downto 0);
signal SAMPLE_AUDIO_IN_SIGNED : SIGNED_AUDIO_TYPE(1 downto 0);
signal SAMPLE_AUDIO_IN_SIGNED : SIGNED_AUDIO_TYPE(3 downto 0);
signal SAMPLE_IRQ : std_logic;
signal SAMPLE_RAM_ADDRESS : std_logic_vector(15 downto 0);
signal SAMPLE_RAM_WRITE_ENABLE : std_logic;
......
signal mixer_r_enable : std_logic;
signal mixer_audio_out_channel : unsigned(2 downto 0);
signal mixer_mute : std_logic;
signal MIXER_SIGNED_REG : SIGNED_AUDIO_TYPE(1 downto 0);
signal MIXER_SIGNED_NEXT : SIGNED_AUDIO_TYPE(1 downto 0);
signal MIX_SEL_NEXT : std_logic_vector(4 downto 0);
signal MIX_SEL_REG : std_logic_vector(4 downto 0);
signal MIXER_SIGNED_REG : SIGNED_AUDIO_TYPE(3 downto 0);
signal MIXER_SIGNED_NEXT : SIGNED_AUDIO_TYPE(3 downto 0);
signal MIX_SEL1_NEXT : std_logic_vector(2 downto 0);
signal MIX_SEL1_REG : std_logic_vector(2 downto 0);
signal MIX_SEL2_NEXT : std_logic_vector(2 downto 0);
signal MIX_SEL2_REG : std_logic_vector(2 downto 0);
-- FLASH
signal flash_do_slow : std_logic_vector(31 downto 0); --58Mhz
......
sample_on : if enable_sample=1 generate
sample1 : entity work.sample_top
GENERIC MAP(
enable_record => enable_routing
)
PORT MAP(
CLK => CLK,
RESET_N => RESET_N,
......
AUDIO_IN0 => SAMPLE_AUDIO_IN_SIGNED(0),
AUDIO_IN1 => SAMPLE_AUDIO_IN_SIGNED(1),
AUDIO_IN2 => SAMPLE_AUDIO_IN_SIGNED(2),
AUDIO_IN3 => SAMPLE_AUDIO_IN_SIGNED(3),
RAM_ADDR => SAMPLE_RAM_ADDRESS,
RAM_WRITE_ENABLE => SAMPLE_RAM_WRITE_ENABLE,
......
CONFIG_ENABLE_REG <= '0';
VERSION_LOC_REG <= (others=>'0');
PAL_REG <= '1';
PSG_FREQ_REG <= "00"; --2MHz
PSG_STEREOMODE_REG <= "01"; --Polish
PSG_PROFILESEL_REG <= "00"; --Simple log
PSG_ENVELOPE16_REG <= '0'; --32 step
SID_FILTER1_REG <= "010"; -- 0=8580,1=6581,2=digifix
SID_FILTER2_REG <= "010"; -- 0=8580,1=6581,2=digifix
if (enable_psg=1) then
PSG_FREQ_REG <= "00"; --2MHz
PSG_STEREOMODE_REG <= "01"; --Polish
PSG_PROFILESEL_REG <= "00"; --Simple log
PSG_ENVELOPE16_REG <= '0'; --32 step
end if;
if (enable_sid=1) then
SID_FILTER1_REG <= "010"; -- 0=8580,1=6581,2=digifix
SID_FILTER2_REG <= "010"; -- 0=8580,1=6581,2=digifix
end if;
RESTRICT_CAPABILITY_REG <= (others=>'1');
CHANNEL_EN_REG <= (others=>'1');
MIXER_SIGNED_REG(0) <= to_signed(0,16);
MIXER_SIGNED_REG(1) <= to_signed(0,16);
MIX_SEL_REG <= (others=>'0');
if (enable_routing=1) then
MIXER_SIGNED_REG(0) <= to_signed(0,16);
MIXER_SIGNED_REG(1) <= to_signed(0,16);
MIXER_SIGNED_REG(2) <= to_signed(0,16);
MIXER_SIGNED_REG(3) <= to_signed(0,16);
MIX_SEL1_REG <= (others=>'0');
MIX_SEL2_REG <= (others=>'0');
end if;
elsif (clk'event and clk='1') then
DETECT_RIGHT_REG <= DETECT_RIGHT_NEXT;
IRQ_EN_REG <= IRQ_EN_NEXT;
......
CONFIG_ENABLE_REG <= CONFIG_ENABLE_NEXT;
VERSION_LOC_REG <= VERSION_LOC_NEXT;
PAL_REG <= PAL_NEXT;
PSG_FREQ_REG <= PSG_FREQ_NEXT;
PSG_STEREOMODE_REG <= PSG_STEREOMODE_NEXT;
PSG_PROFILESEL_REG <= PSG_PROFILESEL_NEXT;
PSG_ENVELOPE16_REG <= PSG_ENVELOPE16_NEXT;
SID_FILTER1_REG <= SID_FILTER1_NEXT;
SID_FILTER2_REG <= SID_FILTER2_NEXT;
if (enable_psg=1) then
PSG_FREQ_REG <= PSG_FREQ_NEXT;
PSG_STEREOMODE_REG <= PSG_STEREOMODE_NEXT;
PSG_PROFILESEL_REG <= PSG_PROFILESEL_NEXT;
PSG_ENVELOPE16_REG <= PSG_ENVELOPE16_NEXT;
end if;
if (enable_sid=1) then
SID_FILTER1_REG <= SID_FILTER1_NEXT;
SID_FILTER2_REG <= SID_FILTER2_NEXT;
end if;
RESTRICT_CAPABILITY_REG <= RESTRICT_CAPABILITY_NEXT;
CHANNEL_EN_REG <= CHANNEL_EN_NEXT;
MIXER_SIGNED_REG <= MIXER_SIGNED_NEXT;
MIX_SEL_REG <= MIX_SEL_NEXT;
if (enable_routing=1) then
MIXER_SIGNED_REG <= MIXER_SIGNED_NEXT;
MIX_SEL1_REG <= MIX_SEL1_NEXT;
MIX_SEL2_REG <= MIX_SEL2_NEXT;
end if;
end if;
end process;
......
RESTRICT_CAPABILITY_REG,
CHANNEL_EN_REG,
PAL_REG,
MIX_SEL_REG
MIX_SEL1_REG, MIX_SEL2_REG
)
begin
SATURATE_NEXT <= SATURATE_REG;
......
PAL_NEXT <= PAL_REG;
MIX_SEL_NEXT <= MIX_SEL_REG;
MIX_SEL1_NEXT <= MIX_SEL1_REG;
MIX_SEL2_NEXT <= MIX_SEL2_REG;
if (CPU_FLASH_COMPLETE='1') then
CPU_FLASH_DATA_NEXT <= flash_do_slow;
......
RESTRICT_CAPABILITY_NEXT <= flash_do_slow(12 downto 8);
-- 13-15 reserved
-- 21-23 reserved (used in sidmax)
MIX_SEL_NEXT(4 downto 0) <= flash_do_slow(20 downto 16); -- (clash with sidmix)
MIX_SEL1_NEXT(2 downto 0) <= flash_do_slow(18 downto 16); -- (clash with sidmix)
MIX_SEL2_NEXT(2 downto 0) <= flash_do_slow(22 downto 20); -- (clash with sidmix)
CHANNEL_EN_NEXT <= flash_do_slow(28 downto 24);
-- 29-31 reserved
when others =>
......
end if;
if (addr_decoded4(4)='1') then
VERSION_LOC_NEXT <= WRITE_DATA(3 downto 0);
VERSION_LOC_NEXT <= WRITE_DATA(2 downto 0);
end if;
if (addr_decoded4(5)='1') then
......
RESTRICT_CAPABILITY_NEXT(4 downto 0) <= WRITE_DATA(4 downto 0);
end if;
if (addr_decoded4(8)='1') then
MIX_SEL_NEXT(4 downto 0) <= WRITE_DATA(4 downto 0);
if enable_routing=1 then
if (addr_decoded4(8)='1') then
MIX_SEL1_NEXT <= WRITE_DATA(2 downto 0);
MIX_SEL2_NEXT <= WRITE_DATA(6 downto 4);
end if;
end if;
if (addr_decoded4(9)='1') then
......
RESTRICT_CAPABILITY_REG,
CHANNEL_EN_REG,
PAL_REG,
MIX_SEL_REG
MIX_SEL1_REG, MIX_SEL2_REG
)
variable ACTUAL_CAPABILITY : std_logic_vector(7 downto 0);
begin
......
end if;
if (enable_sample=1) then
ACTUAL_CAPABILITY(5) := '1';
if sample_ram_size=65536 then
ACTUAL_CAPABILITY(7) := '1';
end if;
else
ACTUAL_CAPABILITY(5) := '0';
end if;
......
else
ACTUAL_CAPABILITY(6) := '0';
end if;
if (enable_routing=1) then
ACTUAL_CAPABILITY(7) := '1';
else
ACTUAL_CAPABILITY(7) := '0';
end if;
if (addr_decoded4(1)='1') then
CONFIG_DO <= ACTUAL_CAPABILITY and "11"&RESTRICT_CAPABILITY_REG(4)&RESTRICT_CAPABILITY_REG;
......
if (addr_decoded4(4)='1') then
-- version
case VERSION_LOC_REG(3 downto 0) is
when "0000" =>
case VERSION_LOC_REG(2 downto 0) is
when "000" =>
CONFIG_DO <= getByte(version,1);
when "0001" =>
when "001" =>
CONFIG_DO <= getByte(version,2);
when "0010" =>
when "010" =>
CONFIG_DO <= getByte(version,3);
when "0011" =>
when "011" =>
CONFIG_DO <= getByte(version,4);
when "0100" =>
when "100" =>
CONFIG_DO <= getByte(version,5);
when "0101" =>
when "101" =>
CONFIG_DO <= getByte(version,6);
when "0110" =>
when "110" =>
CONFIG_DO <= getByte(version,7);
when "0111" =>
when "111" =>
CONFIG_DO <= getByte(version,8);
when "1000" =>
CONFIG_DO <= std_logic_vector(to_unsigned(board/10,4))&std_logic_vector(to_unsigned(board mod 10,4));
when others =>
end case;
end if;
if (addr_decoded4(5)='1') then
CONFIG_DO <= (others=>'0');
CONFIG_DO(1 downto 0) <= PSG_FREQ_REG;
CONFIG_DO(3 downto 2) <= PSG_STEREOMODE_REG;
CONFIG_DO(4) <= PSG_ENVELOPE16_REG;
CONFIG_DO(6 downto 5) <= PSG_PROFILESEL_REG;
if (enable_psg=1) then
if (addr_decoded4(5)='1') then
CONFIG_DO <= (others=>'0');
CONFIG_DO(1 downto 0) <= PSG_FREQ_REG;
CONFIG_DO(3 downto 2) <= PSG_STEREOMODE_REG;
CONFIG_DO(4) <= PSG_ENVELOPE16_REG;
CONFIG_DO(6 downto 5) <= PSG_PROFILESEL_REG;
end if;
end if;
if (addr_decoded4(6)='1') then -- different use on sidmax
CONFIG_DO <= (others=>'0');
CONFIG_DO(2 downto 0) <= SID_FILTER1_REG;
-- (3 downto 3) reserved in case we want more filter options
CONFIG_DO(6 downto 4) <= SID_FILTER2_REG;
-- (7 downto 7) reserved in case we want more filter options
if (enable_sid=1) then
if (addr_decoded4(6)='1') then -- different use on sidmax
CONFIG_DO <= (others=>'0');
CONFIG_DO(2 downto 0) <= SID_FILTER1_REG;
-- (3 downto 3) reserved in case we want more filter options
CONFIG_DO(6 downto 4) <= SID_FILTER2_REG;
-- (7 downto 7) reserved in case we want more filter options
end if;
end if;
if (addr_decoded4(7)='1') then
CONFIG_DO(4 downto 0) <= RESTRICT_CAPABILITY_REG(4 downto 0);
end if;
if (addr_decoded4(8)='1') then -- different use on sidmax
CONFIG_DO(4 downto 0) <= MIX_SEL_REG(4 downto 0);
if (enable_routing=1) then
if (addr_decoded4(8)='1') then -- different use on sidmax
CONFIG_DO(2 downto 0) <= MIX_SEL1_REG;
CONFIG_DO(6 downto 4) <= MIX_SEL2_REG;
end if;
end if;
if (addr_decoded4(9)='1') then
......
AUDIO_3_SIGNED => AUDIO_MIXED_SIGNED(3)
);
routing_on : if enable_routing=1 generate
-- provide audio back to:
-- sample enggine -> to record to ram
-- sid ext -> to use filter (mutes original output)
......
-- S_RIGHT => mixer_r_enable,
-- S_CHANNEL => mixer_audio_out_channel,
process(MIXER_SIGNED_REG, mixer_l_enable, mixer_r_enable, mixer_audio_out, MIX_SEL_REG, mixer_audio_out_channel, SID_FILTER1_REG, SID_FILTER2_REG)
process(MIXER_SIGNED_REG, mixer_l_enable, mixer_r_enable, mixer_audio_out, MIX_SEL1_REG, MIX_SEL2_REG, mixer_audio_out_channel, SID_FILTER1_REG, SID_FILTER2_REG)
begin
MIXER_SIGNED_NEXT <= MIXER_SIGNED_REG;
mixer_mute <= '0';
if (std_logic_vector(mixer_audio_out_channel) = MIX_SEL_REG) then
if (std_logic_vector(mixer_audio_out_channel) = MIX_SEL1_REG) then
if (mixer_l_enable='1') then
MIXER_SIGNED_NEXT(0) <= mixer_audio_out;
mixer_mute <= SID_FILTER1_REG(2);
......
mixer_mute <= SID_FILTER2_REG(2);
end if;
end if;
if (std_logic_vector(mixer_audio_out_channel) = MIX_SEL2_REG) then
if (mixer_l_enable='1') then
MIXER_SIGNED_NEXT(2) <= mixer_audio_out;
end if;
if (mixer_r_enable='1') then
MIXER_SIGNED_NEXT(3) <= mixer_audio_out;
end if;
end if;
end process;
SAMPLE_AUDIO_IN_SIGNED <= MIXER_SIGNED_REG;
SID_AUDIO_IN_SIGNED <= MIXER_SIGNED_REG;
SID_AUDIO_IN_SIGNED(0) <= MIXER_SIGNED_REG(0);
SID_AUDIO_IN_SIGNED(1) <= MIXER_SIGNED_REG(1);
end generate routing_on;
routing_off : if enable_routing=1 generate
SAMPLE_AUDIO_IN_SIGNED(0) <= to_signed(0,16);
SAMPLE_AUDIO_IN_SIGNED(1) <= to_signed(0,16);
SID_AUDIO_IN_SIGNED(0) <= to_signed(0,16);
SID_AUDIO_IN_SIGNED(1) <= to_signed(0,16);
end generate routing_off;
-- sigma delta dither shared component (used in impl 4)
dac_dithergen : entity work.sigmadelta_dither
atari_chips/pokeyv2/sample/top.vhdl
LIBRARY work;
ENTITY sample_top IS
GENERIC
(
enable_record : integer := 0
);
PORT
(
CLK : in std_logic;
......
AUDIO_IN0 : in signed(15 downto 0);
AUDIO_IN1 : in signed(15 downto 0);
AUDIO_IN2 : in signed(15 downto 0);
AUDIO_IN3 : in signed(15 downto 0);
RAM_ADDR : out std_logic_vector(15 downto 0);
RAM_WRITE_ENABLE : out std_logic;
......
signal ram_cpu_write_enable : std_logic;
signal ram_record_write_enable : std_logic;
signal ram_record_enabled_reg : std_logic;
signal ram_record_enabled_next : std_logic;
signal ram_record_source_reg : std_logic;
signal ram_record_source_next : std_logic;
signal ram_record_enabled_reg : std_logic_vector(3 downto 0);
signal ram_record_enabled_next : std_logic_vector(3 downto 0);
signal audio_record : signed(7 downto 0);
signal data_to_write : std_logic_vector(7 downto 0);
signal ch0_start_addr_reg : std_logic_vector(15 downto 0);
......
ram_cpu_addr_reg, ram_data,
irq_en_reg,irq_active_reg,
adpcm_reg,bits8_reg,
ram_record_enabled_reg, ram_record_source_reg
ram_record_enabled_reg
)
begin
DO <= (others=>'0');
......
DO(3 downto 0) <= adpcm_reg;
DO(7 downto 4) <= bits8_reg;
end if;
if (addr_decoded5(20)='1') then
DO(0) <= ram_record_enabled_reg;
DO(1) <= ram_record_source_reg;
if (enable_record = 1) then
if (addr_decoded5(20)='1') then
DO(3 downto 0) <= ram_record_enabled_reg;
end if;
end if;
end process;
......
channel_reg,
irq_en_reg,irq_active_reg,irq_trigger,irq_clear_n,
adpcm_reg, bits8_reg,
ram_record_enabled_reg, ram_record_source_reg
ram_record_enabled_reg
)
begin
ram_cpu_write_enable <= '0';
......
adpcm_next <= adpcm_reg;
ram_record_enabled_next <= ram_record_enabled_reg;
ram_record_source_next <= ram_record_source_reg;
if (write_enable='1') then
if (addr_decoded5(4)='1') then
......
adpcm_next <= DI(3 downto 0);
bits8_next <= DI(7 downto 4);
end if;
if (addr_decoded5(20)='1') then
ram_record_enabled_next <= DI(0);
ram_record_source_next <= DI(1);
if (enable_record = 1) then
if (addr_decoded5(20)='1') then
ram_record_enabled_next <= DI(3 downto 0);
end if;
end if;
end if;
end process;
......
adpcm_reg,
bits8_reg,
adpcm_data_request,
ram_record_source_reg, ram_record_enabled_reg)
ram_record_enabled_reg)
begin
ram_addr <= (others=>'0');
data_nibble <= '0';
......
adpcm_data_ready_next <= adpcm_data_request;
AUDIO_RECORD <= to_signed(0,8);
case adpcm_channel is
when "00" =>
ram_addr <= ch0_addr(16 downto 1);
......
adpcm_on <= adpcm_reg(0);
dma_on <= dma_on_reg(0);
bits8 <= bits8_reg(0);
if (ram_record_enabled_reg ='1') then
ram_record_write_enable <= '1';
if (enable_record=1) then
if (ram_record_enabled_reg(0) ='1') then
ram_record_write_enable <= '1';
end if;
AUDIO_RECORD <= AUDIO_IN0(15 downto 8);
end if;
when "01" =>
ram_addr <= ch1_addr(16 downto 1);
......
adpcm_on <= adpcm_reg(1);
dma_on <= dma_on_reg(1);
bits8 <= bits8_reg(1);
if (enable_record=1) then
if (ram_record_enabled_reg(1) ='1') then
ram_record_write_enable <= '1';
end if;
AUDIO_RECORD <= AUDIO_IN1(15 downto 8);
end if;
when "10" =>
ram_addr <= ch2_addr(16 downto 1);
data_nibble <= ch2_addr(0);
adpcm_on <= adpcm_reg(2);
dma_on <= dma_on_reg(2);
bits8 <= bits8_reg(2);
if (enable_record=1) then
if (ram_record_enabled_reg(2) ='1') then
ram_record_write_enable <= '1';
end if;
AUDIO_RECORD <= AUDIO_IN2(15 downto 8);
end if;
when "11" =>
ram_addr <= ch3_addr(16 downto 1);
data_nibble <= ch3_addr(0);
adpcm_on <= adpcm_reg(3);
dma_on <= dma_on_reg(3);
bits8 <= bits8_reg(3);
if (enable_record=1) then
if (ram_record_enabled_reg(3) ='1') then
ram_record_write_enable <= '1';
end if;
AUDIO_RECORD <= AUDIO_IN3(15 downto 8);
end if;
when others =>
end case;
......
end if;
end process;
process(ram_record_source_reg, request, DI, AUDIO_IN0, AUDIO_IN1)
process(request, DI, AUDIO_RECORD)
begin
DATA_TO_WRITE <= DI;
if (request='0') then
if (ram_record_source_reg='1') then
DATA_TO_WRITE <= std_logic_vector(AUDIO_IN1(15 downto 8));
else
DATA_TO_WRITE <= std_logic_vector(AUDIO_IN0(15 downto 8));
end if;
DATA_TO_WRITE <= std_logic_vector(AUDIO_RECORD);
end if;
end process;
......
bits8_reg <= (others=>'1');
ram_record_enabled_reg <= '0';
ram_record_source_reg <= '0';
if (enable_record = 1) then
ram_record_enabled_reg <= (others=>'0');
end if;
elsif (clk'event and clk='1') then
CH0_REG <= CH0_NEXT;
......
bits8_reg <= bits8_next;
ram_record_enabled_reg <= ram_record_enabled_next;
ram_record_source_reg <= ram_record_source_next;
if (enable_record = 1) then
ram_record_enabled_reg <= ram_record_enabled_next;
end if;
end if;
end process;

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