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< CS0_N : IN STD_LOGIC;
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< POTRESET_N : OUT STD_LOGIC;
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< EXT_INT(18) <= CS0_N;
---
> --EXT_INT(18) <= CS0_N;
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> pot_reset=>potreset,
>
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< POTRESET_N <= not(POTRESET) when ext_clk_enable=0 else '1';
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