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Revision 181

Added by markw about 11 years ago

First cut of mcctv support. No keyboard support yet.

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mcctv/pll_downstream_ntsc.qip
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_ntsc.ppf"]
mcctv/pll_downstream_pal.cmp
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component pll_downstream_pal
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
c4 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
mcctv/pll_downstream_pal.qip
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_downstream_pal.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_pal.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_downstream_pal.ppf"]
mcctv/pll_usb.cmp
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component pll_usb
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
mcctv/pll_usb.vhd
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll_usb.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll_usb IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll_usb;
ARCHITECTURE SYN OF pll_usb IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 3,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 200000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll_usb",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "15.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "15.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_usb.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_usb_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
mcctv/sdram_ctrl_3_ports.cmd
#onerror {resume}
# GAME
#=====================
#run 18871970 ns
#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns
#run 200 ms
mcctv/sdram_ctrl_4_ports.v
`timescale 1 ns / 1 ps
module sdram_ctrl /* verilator tracing_off */
(
//-----------------------------
// Clock and reset
//-----------------------------
input rst, // Global reset
input clk, // Master clock (72 MHz)
output ram_rdy_n, // SDRAM ready
output ram_ref, // SDRAM refresh
output [3:0] ram_cyc, // SDRAM cycles
output [3:0] ram_ph, // SDRAM phases
output [8:0] ram_ph_ctr, // Phase counter
//-----------------------------
// Access bank #0
//-----------------------------
input rden_b0, // Read enable
input wren_b0, // Write enable
input [22:2] addr_b0, // Address (up to 8 MB)
output valid_b0, // Read data valid
output fetch_b0, // Write data fetch
output [15:0] rdata_b0, // Read data
input [15:0] wdata_b0, // Write data
input [1:0] bena_b0, // Byte enable
//-----------------------------
// Access bank #1
//-----------------------------
input rden_b1, // Read enable
input wren_b1, // Write enable
input [22:2] addr_b1, // Address (up to 8 MB)
output valid_b1, // Read data valid
output fetch_b1, // Write data fetch
output [15:0] rdata_b1, // Read data
input [15:0] wdata_b1, // Write data
input [1:0] bena_b1, // Byte enable
//-----------------------------
// Access bank #2
//-----------------------------
input rden_b2, // Read enable
input wren_b2, // Write enable
input [22:2] addr_b2, // Address (up to 8 MB)
output valid_b2, // Read data valid
output fetch_b2, // Write data fetch
output [15:0] rdata_b2, // Read data
input [15:0] wdata_b2, // Write data
input [1:0] bena_b2, // Byte enable
//-----------------------------
// Access bank #3
//-----------------------------
input rden_b3, // Read enable
input wren_b3, // Write enable
input [22:2] addr_b3, // Address (up to 8 MB)
output valid_b3, // Read data valid
output fetch_b3, // Write data fetch
output [15:0] rdata_b3, // Read data
input [15:0] wdata_b3, // Write data
input [1:0] bena_b3, // Byte enable
//-----------------------------
// SDRAM memory signals
//-----------------------------
output sdram_cs_n, // SDRAM chip select
output reg sdram_ras_n, // SDRAM row address strobe
output reg sdram_cas_n, // SDRAM column address strobe
output reg sdram_we_n, // SDRAM write enable
//
output reg [1:0] sdram_ba, // SDRAM bank address
output reg [12:0] sdram_addr, // SDRAM address
//
output reg [3:0] sdram_dqm_n, // SDRAM DQ masks
output reg sdram_dq_oe, // SDRAM data output enable
output reg [31:0] sdram_dq_o, // SDRAM data output
input [31:0] sdram_dq_i // SDRAM data input
);
// SDRAM memory size (16 or 32 MB)
parameter SDRAM_SIZE = 16;
// SDRAM memory width (16 or 32 bits)
parameter SDRAM_WIDTH = 16;
// Clock-to-output delay (for simulation)
parameter Tco_dly = 4.5;
// SDRAM commands
localparam [2:0]
CMD_LMR = 3'b000,
CMD_REF = 3'b001,
CMD_PRE = 3'b010,
CMD_ACT = 3'b011,
CMD_WR = 3'b100,
CMD_RD = 3'b101,
CMD_BST = 3'b110,
CMD_NOP = 3'b111;
// ======================================================
// SDRAM sequencer control
// ======================================================
reg [3:0] r_ram_cyc;
reg [3:0] r_ram_ph;
reg [1:0] r_ba0_ctr;
reg [1:0] r_ba1_ctr;
reg [8:0] r_ph_ctr;
reg [2:0] r_ini_ctr;
reg r_ref_ena;
wire w_bus_eol;
assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
if (rst) begin
r_ram_cyc <= 4'b1000;
r_ram_ph <= 4'b1000;
r_ba0_ctr <= 2'd0;
r_ba1_ctr <= 2'd3;
r_ph_ctr <= 9'd3;
r_ini_ctr <= 3'd0;
r_ref_ena <= 1'b0;
end
else begin
r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
if (r_ram_cyc[3]) begin
r_ram_ph <= { r_ram_ph[2:0], r_ram_ph[3] };
r_ba0_ctr <= r_ba0_ctr + 2'd1;
r_ba1_ctr <= r_ba1_ctr + 2'd1;
// Phase counter : 3 - 288
if (r_ram_ph[3]) begin
r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
end
// Initialization done after 4 scanlines
if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
r_ini_ctr <= r_ini_ctr + 3'd1;
// Refreshes are enabled during phase 284 - 288
//r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
r_ref_ena <= r_ram_ph[1]; // r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
end
end
end
assign ram_ref = r_ref_ena;
assign ram_cyc = r_ram_cyc;
assign ram_ph = r_ram_ph;
assign ram_ph_ctr = r_ph_ctr;
assign ram_rdy_n = ~r_ini_ctr[2];
// ======================================================
// SDRAM phase generation
// ======================================================
reg [3:0] r_rd_act;
reg [3:0] r_wr_act;
reg r_act_ph; // Activate phase
reg r_rd_ph; // Burst read phase
reg r_wr_ph; // Burst write phase
reg r_ref_ph; // Auto-refresh phase
reg [3:0] r_ini_ph; // Initialization phases
reg r_pre_ph; // Precharge phase
reg r_lmr_ph; // Load mode register phase
always@(posedge rst or posedge clk) begin : PHASE_GEN
if (rst) begin
r_rd_act <= 4'b0000;
r_wr_act <= 4'b0000;
r_act_ph <= 1'b0;
r_rd_ph <= 1'b0;
r_wr_ph <= 1'b0;
r_ref_ph <= 1'b0;
r_ini_ph <= 4'b0000;
r_pre_ph <= 1'b0;
r_lmr_ph <= 1'b0;
end
else begin
if (r_ram_cyc[0]) begin
// Access port #0 read/write
if (r_ram_ph[0]) begin
r_rd_act[0] <= rden_b0 & ~r_ref_ena;
r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
end
else if (r_ram_ph[2]) begin
r_rd_act[0] <= 1'b0;
r_wr_act[0] <= 1'b0;
end
// Access port #1 read/write
if (r_ram_ph[1]) begin
r_rd_act[1] <= rden_b1 & ~r_ref_ena;
r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
end
else if (r_ram_ph[3]) begin
r_rd_act[1] <= 1'b0;
r_wr_act[1] <= 1'b0;
end
// Access port #2 read/write
if (r_ram_ph[2]) begin
r_rd_act[2] <= rden_b2 & ~r_ref_ena;
r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
end
else if (r_ram_ph[0]) begin
r_rd_act[2] <= 1'b0;
r_wr_act[2] <= 1'b0;
end
// Access port #3 read/write
if (r_ram_ph[3]) begin
r_rd_act[3] <= rden_b3 & ~r_ref_ena;
r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
end
else if (r_ram_ph[1]) begin
r_rd_act[3] <= 1'b0;
r_wr_act[3] <= 1'b0;
end
end
if (r_ram_cyc[0] & r_ini_ctr[2]) begin
// Activate phase
r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
| (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
| (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
| (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
end
if (r_ram_cyc[3] & r_ini_ctr[2]) begin
// Read phase
r_rd_ph <= (r_ram_ph[0] & r_rd_act[0])
| (r_ram_ph[1] & r_rd_act[1])
| (r_ram_ph[2] & r_rd_act[2])
| (r_ram_ph[3] & r_rd_act[3]);
// Write phase
r_wr_ph <= (r_ram_ph[0] & r_wr_act[0])
| (r_ram_ph[1] & r_wr_act[1])
| (r_ram_ph[2] & r_wr_act[2])
| (r_ram_ph[3] & r_wr_act[3]);
end
// Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
if (r_ram_cyc[3] & r_ram_ph[2]) begin
if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
end
else begin
r_ini_ph <= 4'b0000;
end
end
// Precharge phase
r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
// Refresh phase
//r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
// | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0]; // Init
r_ref_ph <= r_ref_ena & r_ini_ctr[2] // Normal
| (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0]; // Init
// Load mode register phase
r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
end
end
// ======================================================
// SDRAM address generation
// ======================================================
reg [22:2] r_addr_mux;
reg [10:2] r_addr_col;
reg [12:0] r_addr_sdr;
reg [1:0] r_ba_sdr;
always@(posedge rst or posedge clk) begin : ADDRESS_GEN
if (rst) begin
r_addr_mux <= 21'd0;
r_addr_col <= 9'd0;
r_addr_sdr <= 13'd0;
r_ba_sdr <= 2'b00;
end
else begin
// Port address multiplexer
if (r_ram_cyc[0]) begin
r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
| addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
| addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
| addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
end
// Column address (for read/write op.)
if (r_ram_cyc[3]) begin
r_addr_col <= r_addr_mux[10:2];
end
// Memories layouts :
// ------------------
// SDRAM 4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
// SDRAM 8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
// SDRAM 8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
// SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
// Row / col address
if (SDRAM_WIDTH == 32) begin
// 32-bit bus
if (SDRAM_SIZE == 32) begin
// 32 MB
r_addr_sdr <= { 4'b0000, r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph & r_ram_cyc[0]}} // 512 cols
| { 1'b0, r_addr_mux[22:11] } & {13{r_act_ph & r_ram_cyc[1]}} // 4096 rows
| { 4'b0010, r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph & r_ram_cyc[2]}} // 512 cols
| { 4'b0010, r_addr_col[10: 2] } & {13{r_wr_ph & r_ram_cyc[3]}} // 512 cols
| { 3'b001, 10'b000000000 } & {13{r_ini_ph[0] }} // Init : precharge all
| { 3'b000, 10'b1_00_010_0_000 } & {13{r_ini_ph[3] }}; // Init : load mode register (BL=1, CAS=2)
end
else begin
// 16 MB
r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph & r_ram_cyc[0]}} // 256 cols
| { 1'b0, r_addr_mux[21:10] } & {13{r_act_ph & r_ram_cyc[1]}} // 4096 rows
| { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph & r_ram_cyc[2]}} // 256 cols
| { 5'b00100, r_addr_col[ 9: 2] } & {13{r_wr_ph & r_ram_cyc[3]}} // 256 cols
| { 3'b001, 10'b000000000 } & {13{r_ini_ph[0] }} // Init : precharge all
| { 3'b000, 10'b1_00_010_0_000 } & {13{r_ini_ph[3] }}; // Init : load mode register (BL=1, CAS=2)
end
end
else begin
// 16-bit bus
if (SDRAM_SIZE == 32) begin
// 32 MB
r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph & r_ram_cyc[0]}} // 512 cols
| r_addr_mux[22:10] & {13{r_act_ph & r_ram_cyc[1]}} // 8192 rows
| { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph & r_ram_cyc[2]}} // 512 cols
| { 4'b0010, r_addr_col[9:2], 1'b0 } & {13{r_wr_ph & r_ram_cyc[3]}} // 512 cols
| { 3'b001, 10'b000000000 } & {13{r_ini_ph[0] }} // Init : precharge all
| { 3'b000, 10'b1_00_010_0_001 } & {13{r_ini_ph[3] }}; // Init : load mode register (BL=2, CAS=2)
end
else begin
// 16 MB
r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph & r_ram_cyc[0]}} // 512 cols
| { 1'b0, r_addr_mux[21:10] } & {13{r_act_ph & r_ram_cyc[1]}} // 4096 rows
| { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph & r_ram_cyc[2]}} // 512 cols
| { 4'b0010, r_addr_col[9:2], 1'b0 } & {13{r_wr_ph & r_ram_cyc[3]}} // 512 cols
| { 3'b001, 10'b000000000 } & {13{r_ini_ph[0] }} // Init : precharge all
| { 3'b000, 10'b0_00_010_0_001 } & {13{r_ini_ph[3] }}; // Init : load mode register (BL=2, CAS=2)
end
end
// Bank address
r_ba_sdr <= r_ba1_ctr & {2{r_rd_ph & r_ram_cyc[0]}} // 32-bit read
| r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}} // Activate
| r_ba1_ctr & {2{r_rd_ph & r_ram_cyc[2]}} // 32-bit read with auto-precharge
| r_ba1_ctr & {2{r_wr_ph & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
end
end
// ======================================================
// SDRAM command generation
// ======================================================
reg [2:0] r_cmd_sdr;
always@(posedge rst or posedge clk) begin : COMMAND_GEN
reg [2:0] v_cmd_0;
reg [2:0] v_cmd_1;
reg [2:0] v_cmd_2;
reg [2:0] v_cmd_3;
reg [2:0] v_cmd_4;
reg [2:0] v_cmd_5;
reg [2:0] v_cmd_6;
if (rst) begin
r_cmd_sdr <= CMD_NOP;
end
else begin
v_cmd_0 = CMD_RD | {3{~r_rd_ph }};
v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
v_cmd_2 = CMD_RD | {3{~r_rd_ph }};
v_cmd_3 = CMD_WR | {3{~r_wr_ph }};
v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
& (v_cmd_1 | {3{~r_ram_cyc[1]}})
& (v_cmd_2 | {3{~r_ram_cyc[2]}})
& (v_cmd_3 | {3{~r_ram_cyc[3]}})
& (v_cmd_4 | {3{~r_ram_cyc[3]}})
& (v_cmd_5 | {3{~r_ram_cyc[3]}})
& (v_cmd_6 | {3{~r_ram_cyc[3]}});
end
end
assign sdram_cs_n = 1'b0;
// Command and address
/* verilator lint_off STMTDLY */
always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
always@(*) sdram_we_n = #Tco_dly r_cmd_sdr[0];
always@(*) sdram_ba = #Tco_dly r_ba_sdr;
always@(*) sdram_addr = #Tco_dly r_addr_sdr;
/* verilator lint_on STMTDLY */
// ======================================================
// Data being read
// ======================================================
reg [3:0] r_data_vld;
reg r_data_sel;
reg [15:0] r_lrdata_p0;
reg [15:0] r_hrdata_p0;
reg [15:0] r_hrdata_p1;
wire [15:0] w_rdata_p0;
always@(posedge rst or posedge clk) begin : DATA_READ
if (rst) begin
r_data_vld <= 4'b0000;
r_data_sel <= 1'b0;
r_lrdata_p0 <= 16'h0000;
r_hrdata_p0 <= 16'h0000;
r_hrdata_p1 <= 16'h0000;
end
else begin
if (r_ram_cyc[3]) begin
r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
end
r_data_sel <= r_ram_cyc[1] | r_ram_cyc[3];
r_lrdata_p0 <= sdram_dq_i[15:0];
r_hrdata_p0 <= sdram_dq_i[31:16];
r_hrdata_p1 <= r_hrdata_p0;
end
end
// 32-bit to 16-bit multiplexer
assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
// Access Port #0
assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
assign valid_b0 = r_data_vld[0];
// Access Port #1
assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
assign valid_b1 = r_data_vld[1];
// Access Port #2
assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
assign valid_b2 = r_data_vld[2];
// Access Port #3
assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
assign valid_b3 = r_data_vld[3];
// ======================================================
// Data being written
// ======================================================
reg [3:0] r_data_fe_p0;
reg [3:0] r_data_fe_p1;
reg r_data_oe;
reg [15:0] r_wdata_p2a;
reg [15:0] r_wdata_p2b;
reg [31:0] r_wdata_p3;
reg [1:0] r_bena_p2a;
reg [1:0] r_bena_p2b;
reg [3:0] r_bena_p3;
always@(posedge rst or posedge clk) begin : DATA_WRITE
if (rst) begin
r_data_fe_p0 <= 4'b0000;
r_data_fe_p1 <= 4'b0000;
r_data_oe <= 1'b0;
r_wdata_p2a <= 16'h0000;
r_wdata_p2b <= 16'h0000;
r_wdata_p3 <= 32'h0000_0000;
r_bena_p2a <= 2'b00;
r_bena_p2b <= 2'b00;
r_bena_p3 <= 4'b00_00;
end
else begin
if (r_ram_cyc[3]) begin
r_data_fe_p0 <= r_wr_act & r_ram_ph;
r_data_oe <= r_wr_ph;
end
else if (r_ram_cyc[1]) begin
r_data_fe_p0 <= 4'b0000;
r_data_oe <= 1'b0;
end
r_data_fe_p1 <= r_data_fe_p0;
if (SDRAM_WIDTH == 32) begin
// 16-bit -> 32-bit bus
if (r_data_sel) begin
r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
| wdata_b1 & {16{r_data_fe_p1[1]}}
| wdata_b2 & {16{r_data_fe_p1[2]}}
| wdata_b3 & {16{r_data_fe_p1[3]}};
r_bena_p2b <= bena_b0 & {2{r_data_fe_p1[0]}}
| bena_b1 & {2{r_data_fe_p1[1]}}
| bena_b2 & {2{r_data_fe_p1[2]}}
| bena_b3 & {2{r_data_fe_p1[3]}}
| {2{~|r_data_fe_p1}};
end
else begin
r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
| wdata_b1 & {16{r_data_fe_p1[1]}}
| wdata_b2 & {16{r_data_fe_p1[2]}}
| wdata_b3 & {16{r_data_fe_p1[3]}};
r_bena_p2a <= bena_b0 & {2{r_data_fe_p1[0]}}
| bena_b1 & {2{r_data_fe_p1[1]}}
| bena_b2 & {2{r_data_fe_p1[2]}}
| bena_b3 & {2{r_data_fe_p1[3]}}
| {2{~|r_data_fe_p1}};
end
r_wdata_p3 <= { r_wdata_p2b, r_wdata_p2a };
r_bena_p3 <= { r_bena_p2b, r_bena_p2a };
end
else begin
// 16-bit bus
r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
| wdata_b1 & {16{r_data_fe_p1[1]}}
| wdata_b2 & {16{r_data_fe_p1[2]}}
| wdata_b3 & {16{r_data_fe_p1[3]}};
r_wdata_p2b <= r_wdata_p2a;
r_wdata_p3 <= { 16'h0000, r_wdata_p2b };
r_bena_p2a <= bena_b0 & {2{r_data_fe_p1[0]}}
| bena_b1 & {2{r_data_fe_p1[1]}}
| bena_b2 & {2{r_data_fe_p1[2]}}
| bena_b3 & {2{r_data_fe_p1[3]}}
| {2{~|r_data_fe_p1}};
r_bena_p2b <= r_bena_p2a;
r_bena_p3 <= { 2'b00, r_bena_p2b };
end
end
end
// Output mask, data & enable
/* verilator lint_off STMTDLY */
always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
always@(*) sdram_dq_o = #Tco_dly r_wdata_p3;
always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
/* verilator lint_on STMTDLY */
// Access Port #0
assign fetch_b0 = r_data_fe_p0[0];
// Access Port #1
assign fetch_b1 = r_data_fe_p0[1];
// Access Port #2
assign fetch_b2 = r_data_fe_p0[2];
// Access Port #3
assign fetch_b3 = r_data_fe_p0[3];
endmodule /* verilator tracing_on */
mcctv/svideo/sin_cos.vhd
-- ===================================================================================
-- Package / Component definition
-- ===================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE sin_cos_pkg IS
COMPONENT sin_cos
PORT(
-- Clock
clk : IN STD_LOGIC;
clk_ena : IN STD_LOGIC;
-- Sine computation
sin_ph : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sin_amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sin_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
-- Cosine computation
cos_ph : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cos_amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cos_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END COMPONENT;
END PACKAGE;
-- ===================================================================================
-- Entity / Architecture definition
-- ===================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sin_cos IS
PORT(
-- Clock
clk : IN STD_LOGIC;
clk_ena : IN STD_LOGIC;
-- Sine computation
sin_ph : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
sin_amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sin_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
-- Cosine computation
cos_ph : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cos_amp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cos_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
);
END sin_cos;
ARCHITECTURE rtl OF sin_cos IS
COMPONENT sin_rom IS
PORT
(
clock : IN STD_LOGIC;
enable : IN STD_LOGIC := '1';
address_a : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT sin_rom;
SIGNAL sin_val : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL cos_val : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL sin_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL cos_ph_dly : STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
sin_inst : sin_rom
PORT MAP
(
clock => clk,
enable => clk_ena,
address_a(10 DOWNTO 3) => sin_amp,
address_a(2) => sin_ph(2) XOR sin_ph(3),
address_a(1) => sin_ph(1) XOR sin_ph(3),
address_a(0) => sin_ph(0) XOR sin_ph(3),
q_a => sin_val(7 DOWNTO 0),
address_b(10 DOWNTO 3) => cos_amp,
address_b(2) => cos_ph(2) XOR (NOT cos_ph(3)),
address_b(1) => cos_ph(1) XOR (NOT cos_ph(3)),
address_b(0) => cos_ph(0) XOR (NOT cos_ph(3)),
q_b => cos_val(7 DOWNTO 0)
);
sin_val(8) <= '0';
cos_val(8) <= '0';
-- Delayed phase for output generation
sin_ph_dly <= sin_ph WHEN rising_edge(clk);
cos_ph_dly <= cos_ph WHEN rising_edge(clk);
-- Output generation using sine and cosine symetries
sin_cos_gen:
FOR i IN 0 TO 8 GENERATE
sin_out(i) <= sin_val(i) XOR sin_ph_dly(4);
cos_out(i) <= cos_val(i) XOR cos_ph_dly(3) XOR cos_ph_dly(4);
END GENERATE;
END rtl;
mcctv/MCCTV_Atari800XL_v0.6_release.txt
===========================================
MCCTV Atari 800XL core v0.60 release note
===========================================
Mark Watson
scrameta@gmail.com
-------------------------------------------
All control is via the MCC controller.
Currently games are limited to those that can be played with start/select/option/reset and joystick.
Special/console keys (joystick 1):
Start button or button 4 - Start
Select button or button 3 - Select
button 2 - Option
left shoulder 1 - Reset
left shoulder 2 - Cold start (clear base 64KB RAM and reset)
right shoulder 1 - Select drive 1 and cold start
Use joystick to make selection in menu
Left - up several lines
Right - down several lines
Up - up 1 line
Down - down 1 line
Fire - select
Remember many titles require holding 'option'
Select "DIR .." to go up a directory
Select "DIR xxx" to go down a directory
right shoulder 2 - System settings menu
Use joystick to make selection
Turbo - system speed
Left/right to select
1x (default): is very compatible - speed closely matches original hardware ~1.7MHz
2x: ~3.4MHz - less compatible
4x: ~6.8MHz - less compatible
8x/16x: 13MHz, 27MHZ - limited by SDRAM latency, not quicker than 4x yet.
RAM
Left/right to select
64KB: like 65XE
128KB: like 130XE, 64KB ext ram, switchable by antic/cpu
320KB(Compy shop)(default): 256KB ext ram, switchable by antic/cpu
320KB(Rambo): 256KB ext ram, both antic/cpu switch together
576KB(Compy shop): 512KB ext ram, switchable by antic/cpu
576KB(Rambo): 512KB ext ram, both antic/cpu switch together
1088KB: 1024KB ext ram, both antic/cpu switch together
4160KB: - very imcompatible!
ROM
Right/fire: File selector
Select a different system OS ROM - can by 16KB or 10KB
Drive
Left: Remove disk
Right: File selector
Fire: Put this disk in F1
Cartridge 8K simple
Fire: select file
This allows a ROM to be loaded in the place of BASIC
Some simple ROM cartridges can be used
This is temporary until proper cartridge support is implemented
System ROM:
Loaded from /System/rom/atari800/atarixl.rom
Basic:
Loaded from /System/rom/atari800/ataribas.rom
Disk images:
Default dir: /atari800/user
Supported types:
.ATR - Atari disk image with header. single/medium/double density.
.XFD - Atari disk image without header.
.XEX - Atari executable. A simple bootloader is loaded, not 100% compatible.
Important notes:
When running Atari software a lot of programs need to have basic disable. Hold option when pressing reset.
Features
* Acid 800 test pass
* 99% of software runs
* Version for PAL/NTSC VGA/SVIDEO
* Write support
* Drive emulation
Known issues
* No keyboard support yet
* ~1% of programs fail
* Copymate write verify fails
* Entering menu during disk access may hang ZPU (used for drive emulation/menus)
* Hardware matches Atari very closely - including overscan corruption - this often shows up on VGA monitors.
* Cartridge support may be broken
Enjoy !
mcctv/TODO
Merge with mcc216 core - with generic to select composite, sdram size, keyboard/usb etc.
USB keyboard support?
On screen keyboard support?
mcctv/atari800core.jdi
<sld_project_info>
<project>
<hash md5_digest_80b="00000000000000000000"/>
</project>
<file_info/>
</sld_project_info>
mcctv/atari800core.qpf
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2012 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
# Date created = 13:58:38 April 11, 2013
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "12.1"
DATE = "13:58:38 April 11, 2013"
# Revisions
PROJECT_REVISION = "atari800core"
mcctv/atari800core.qsf
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 132 02/25/2009 SJ Web Edition
# Date created = 20:12:08 December 25, 2009
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# atari800core_mcc_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name DEVICE EP4CE15E22C7
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY atari800core_mcc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:12:08 DECEMBER 25, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS128
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name SIMULATION_MODE TIMING
set_location_assignment PIN_46 -to AUDIO_L
set_location_assignment PIN_49 -to AUDIO_R
set_location_assignment PIN_55 -to FPGA_CLK
set_location_assignment PIN_42 -to SD_CLK
set_location_assignment PIN_43 -to SD_CMD
set_location_assignment PIN_44 -to SD_DAT3
set_location_assignment PIN_52 -to SD_DAT0
set_location_assignment PIN_59 -to SDRAM_A[0]
set_location_assignment PIN_58 -to SDRAM_A[1]
set_location_assignment PIN_51 -to SDRAM_A[2]
set_location_assignment PIN_50 -to SDRAM_A[3]
set_location_assignment PIN_132 -to SDRAM_A[4]
set_location_assignment PIN_125 -to SDRAM_A[5]
set_location_assignment PIN_121 -to SDRAM_A[6]
set_location_assignment PIN_120 -to SDRAM_A[7]
set_location_assignment PIN_119 -to SDRAM_A[8]
set_location_assignment PIN_115 -to SDRAM_A[9]
set_location_assignment PIN_60 -to SDRAM_A[10]
set_location_assignment PIN_114 -to SDRAM_A[11]
set_location_assignment PIN_113 -to SDRAM_A[12]
set_location_assignment PIN_111 -to SDRAM_CLK
set_location_assignment PIN_110 -to SDRAM_DQMH_n
set_location_assignment PIN_71 -to SDRAM_DQML_n
set_location_assignment PIN_106 -to SDRAM_DQ[8]
set_location_assignment PIN_105 -to SDRAM_DQ[9]
set_location_assignment PIN_104 -to SDRAM_DQ[10]
set_location_assignment PIN_103 -to SDRAM_DQ[11]
set_location_assignment PIN_101 -to SDRAM_DQ[12]
set_location_assignment PIN_100 -to SDRAM_DQ[13]
set_location_assignment PIN_99 -to SDRAM_DQ[14]
set_location_assignment PIN_98 -to SDRAM_DQ[15]
set_location_assignment PIN_72 -to SDRAM_DQ[7]
set_location_assignment PIN_76 -to SDRAM_DQ[6]
set_location_assignment PIN_77 -to SDRAM_DQ[5]
set_location_assignment PIN_80 -to SDRAM_DQ[4]
set_location_assignment PIN_83 -to SDRAM_DQ[3]
set_location_assignment PIN_85 -to SDRAM_DQ[2]
set_location_assignment PIN_86 -to SDRAM_DQ[1]
set_location_assignment PIN_87 -to SDRAM_DQ[0]
set_location_assignment PIN_68 -to SDRAM_CAS_n
set_location_assignment PIN_66 -to SDRAM_CS_n
set_location_assignment PIN_64 -to SDRAM_BA[1]
set_location_assignment PIN_65 -to SDRAM_BA[0]
set_location_assignment PIN_67 -to SDRAM_RAS_n
set_location_assignment PIN_69 -to SDRAM_WE_n
set_location_assignment PIN_112 -to SDRAM_CKE
set_location_assignment PIN_144 -to VGA_G[0]
set_location_assignment PIN_143 -to VGA_G[1]
set_location_assignment PIN_142 -to VGA_G[2]
set_location_assignment PIN_141 -to VGA_G[3]
set_location_assignment PIN_137 -to VGA_B[0]
set_location_assignment PIN_136 -to VGA_B[1]
set_location_assignment PIN_135 -to VGA_B[2]
set_location_assignment PIN_133 -to VGA_B[3]
set_location_assignment PIN_12 -to CFG_CLK
set_location_assignment PIN_8 -to CFG_CS_n
set_location_assignment PIN_13 -to CFG_DIN
set_location_assignment PIN_6 -to CFG_DOUT
set_location_assignment PIN_31 -to dplus1
set_location_assignment PIN_30 -to dminus1
set_location_assignment PIN_33 -to dplus2
set_location_assignment PIN_32 -to dminus2
set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name USE_SIGNALTAP_FILE atari.stp
set_location_assignment PLL_2 -to "clk_reset:clk_rst_inst|pll_main:main_inst"
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQMH_n
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQML_n
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ALWAYS
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name IGNORE_CASCADE_BUFFERS ON
set_location_assignment PLL_4 -to "clk_reset:clk_rst_inst|pll_5M_pal_ntsc:pll_5m_inst" -disable
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name QIP_FILE pll_usb.qip
set_global_assignment -name QIP_FILE pal_pll.qip
set_global_assignment -name QIP_FILE pll_downstream_pal.qip
set_global_assignment -name QIP_FILE ntsc_pll.qip
set_global_assignment -name QIP_FILE pll_downstream_ntsc.qip
set_global_assignment -name SDC_FILE atari800core.sdc
set_global_assignment -name VERILOG_FILE sdram_ctrl_3_ports.v
set_global_assignment -name VHDL_FILE zpu_rom.vhdl
set_global_assignment -name VHDL_FILE atari800core_mcc.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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