EclaireXL

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<messages>

<msg type="info" file="sim" num="172" delta="old" >Generating IP...

</msg>

<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>

</msg>

<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>

</msg>

<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for VHDL synthesis</arg>

</msg>

<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.

</msg>

<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.

</msg>

</messages>