EclaireXL

REM file: simulate_mti.bat

REM

REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

REM

REM This file contains confidential and proprietary information

REM of Xilinx, Inc. and is protected under U.S. and

REM international copyright and other intellectual property

REM laws.

REM

REM DISCLAIMER

REM This disclaimer is not a license and does not grant any

REM rights to the materials distributed herewith. Except as

REM otherwise provided in a valid license issued to you by

REM Xilinx, and to the maximum extent permitted by applicable

REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

REM (2) Xilinx shall not be liable (whether in contract or tort,

REM including negligence, or under any other theory of

REM liability) for any loss or damage of any kind or nature

REM related to, arising under or in connection with these

REM materials, including for any direct, or any indirect,

REM special, incidental, or consequential loss or damage

REM (including loss of data, profits, goodwill, or any type of

REM loss or damage suffered as a result of any action brought

REM by a third party) even if such damage or loss was

REM reasonably foreseeable or Xilinx had been advised of the

REM possibility of the same.

REM

REM CRITICAL APPLICATIONS

REM Xilinx products are not designed or intended to be fail-

REM safe, or for use in any application requiring fail-safe

REM performance, such as life-support or safety devices or

REM systems, Class III medical devices, nuclear facilities,

REM applications related to the deployment of airbags, or any

REM other applications that could lead to death, personal

REM injury, or severe property or environmental damage

REM (individually and collectively, "Critical

REM Applications"). Customer assumes the sole risk and

REM liability of any use of Xilinx products in Critical

REM Applications, subject only to applicable laws and

REM regulations governing limitations on product liability.

REM

REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

REM PART OF THIS FILE AT ALL TIMES.

REM

REM set up the working directory

vlib work

REM compile all of the files

vcom -work work ..\..\..\pll_ntsc.vhd

vcom -work work ..\..\example_design\pll_ntsc_exdes.vhd

vcom -work work ..\pll_ntsc_tb.vhd

REM run the simulation

vsim -c -t ps -voptargs="+acc" -L secureip -L unisim work.pll_ntsc_tb

COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",

SCOPE = :dut;

REM file: simulate_mti.bat

REM

REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

REM

REM This file contains confidential and proprietary information

REM of Xilinx, Inc. and is protected under U.S. and

REM international copyright and other intellectual property

REM laws.

REM

REM DISCLAIMER

REM This disclaimer is not a license and does not grant any

REM rights to the materials distributed herewith. Except as

REM otherwise provided in a valid license issued to you by

REM Xilinx, and to the maximum extent permitted by applicable

REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

REM (2) Xilinx shall not be liable (whether in contract or tort,

REM including negligence, or under any other theory of

REM liability) for any loss or damage of any kind or nature

REM related to, arising under or in connection with these

REM materials, including for any direct, or any indirect,

REM special, incidental, or consequential loss or damage

REM (including loss of data, profits, goodwill, or any type of

REM loss or damage suffered as a result of any action brought

REM by a third party) even if such damage or loss was

REM reasonably foreseeable or Xilinx had been advised of the

REM possibility of the same.

REM

REM CRITICAL APPLICATIONS

REM Xilinx products are not designed or intended to be fail-

REM safe, or for use in any application requiring fail-safe

REM performance, such as life-support or safety devices or

REM systems, Class III medical devices, nuclear facilities,

REM applications related to the deployment of airbags, or any

REM other applications that could lead to death, personal

REM injury, or severe property or environmental damage

REM (individually and collectively, "Critical

REM Applications"). Customer assumes the sole risk and

REM liability of any use of Xilinx products in Critical

REM Applications, subject only to applicable laws and

REM regulations governing limitations on product liability.

REM

REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

REM PART OF THIS FILE AT ALL TIMES.

REM

# set up the working directory

set work work

vlib work

REM compile all of the files

vcom -work work ..\..\implement\results\routed.vhd

vcom -work work pll_ntsc_tb.vhd

REM run the simulation

vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprim -sdfmax pll_ntsc_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.pll_ntsc_tb

gen_tv_pal : if tv=1 generate

pll : entity work.pll_pal

port map (

CLK_IN1 => CLK_32,

CLK_OUT1 => CLK,

RESET => '0',

LOCKED => PLL_LOCKED );

end generate;

gen_tv_ntsc : if tv=0 generate

pll : entity work.pll_ntsc

port map (

CLK_IN1 => CLK_32,

CLK_OUT1 => CLK,

RESET => '0',

LOCKED => PLL_LOCKED );

end generate;

process(clk,reset_n)

elsif (clk'event and clk='1') then

CLK => CLK,

vhdl work "pll_pal.vhd"

vhdl work "pll_ntsc.vhd"

#/bin/sh

# file: simulate_mti.sh

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# set up the working directory

set work work

vlib work

# compile all of the files

vcom -work work ../../../pll_ntsc.vhd

vcom -work work ../../example_design/pll_ntsc_exdes.vhd

vcom -work work ../pll_ntsc_tb.vhd

# run the simulation

vsim -c -t ps -voptargs="+acc" -L secureip -L unisim work.pll_ntsc_tb

#!/bin/sh

# file: simulate_vcs.sh

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# remove old files

rm -rf simv* csrc DVEfiles AN.DB

# compile all of the files

# Note that -sverilog is not strictly required- You can

# remove the -sverilog if you change the type of the

# localparam for the periods in the testbench file to

# [63:0] from time

vhdlan -xlrm ../../../pll_ntsc.vhd \

../../example_design/pll_ntsc_exdes.vhd \

../pll_ntsc_tb.vhd

# prepare the simulation

vcs +vcs+lic+wait -xlrm -debug pll_ntsc_tb

# run the simulation

./simv -xlrm -ucli -i ucli_commands.key

# launch the viewer

#dve -vpd vcdplus.vpd -session vcs_session.tcl

# file: wave.sv

#

# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# Get the windows set up

#

if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {

window geometry "Design Browser 1" 1054x819+536+322

}

window target "Design Browser 1" on

browser using {Design Browser 1}

browser set \

-scope nc::pll_ntsc_tb

browser yview see nc::pll_ntsc_tb

browser timecontrol set -lock 0

if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {

window geometry "Waveform 1" 1010x600+0+541

}

window target "Waveform 1" on

waveform using {Waveform 1}

waveform sidebar visibility partial

waveform set \

-primarycursor TimeA \

-signalnames name \

-signalwidth 175 \

-units ns \

-valuewidth 75

cursor set -using TimeA -time 0

waveform baseline set -time 0

waveform xview limits 0 20000n

#

# Define signal groups

#

catch {group new -name {Output clocks} -overlay 0}

catch {group new -name {Status/control} -overlay 0}

catch {group new -name {Counters} -overlay 0}

set id [waveform add -signals [list {nc::pll_ntsc_tb.CLK_IN1}]]

group using {Output clocks}

group set -overlay 0

group set -comment {}

group clear 0 end

group insert \

{pll_ntsc_tb.dut.clk} \

group using {Counters}

group set -overlay 0

group set -comment {}

group clear 0 end

group insert \

{pll_ntsc_tb.dut.counter} \

group using {Status/control}

group set -overlay 0

group set -comment {}

group clear 0 end

group insert \

{nc::pll_ntsc_tb.RESET} {nc::pll_ntsc_tb.LOCKED}

set id [waveform add -signals [list {nc::pll_ntsc_tb.COUNT} ]]

set id [waveform add -signals [list {nc::pll_ntsc_tb.test_phase} ]]

waveform format $id -radix %a

set groupId [waveform add -groups {{Input clocks}}]

set groupId [waveform add -groups {{Output clocks}}]

set groupId [waveform add -groups {{Status/control}}]

set groupId [waveform add -groups {{Counters}}]

-- file: pll_ntsc_tb.vhd

--

-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

--

-- This file contains confidential and proprietary information

-- of Xilinx, Inc. and is protected under U.S. and

-- international copyright and other intellectual property

-- laws.

--

-- DISCLAIMER

-- This disclaimer is not a license and does not grant any

-- rights to the materials distributed herewith. Except as

-- otherwise provided in a valid license issued to you by

-- Xilinx, and to the maximum extent permitted by applicable

-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

-- (2) Xilinx shall not be liable (whether in contract or tort,

-- including negligence, or under any other theory of

-- liability) for any loss or damage of any kind or nature

-- related to, arising under or in connection with these

-- materials, including for any direct, or any indirect,

-- special, incidental, or consequential loss or damage

-- (including loss of data, profits, goodwill, or any type of

-- loss or damage suffered as a result of any action brought

-- by a third party) even if such damage or loss was

-- reasonably foreseeable or Xilinx had been advised of the

-- possibility of the same.

--

-- CRITICAL APPLICATIONS

-- Xilinx products are not designed or intended to be fail-

-- safe, or for use in any application requiring fail-safe

-- performance, such as life-support or safety devices or

-- systems, Class III medical devices, nuclear facilities,

-- applications related to the deployment of airbags, or any

-- other applications that could lead to death, personal

-- injury, or severe property or environmental damage

-- (individually and collectively, "Critical

-- Applications"). Customer assumes the sole risk and

-- liability of any use of Xilinx products in Critical

-- Applications, subject only to applicable laws and

-- regulations governing limitations on product liability.

--

-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

-- PART OF THIS FILE AT ALL TIMES.

--

------------------------------------------------------------------------------

-- Clocking wizard demonstration testbench

------------------------------------------------------------------------------

-- This demonstration testbench instantiates the example design for the

-- clocking wizard. Input clocks are toggled, which cause the clocking

-- network to lock and the counters to increment.

------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

use ieee.std_logic_textio.all;

library std;

use std.textio.all;

library work;

use work.all;

entity pll_ntsc_tb is

end pll_ntsc_tb;

architecture test of pll_ntsc_tb is

-- Clock to Q delay of 100 ps

constant TCQ : time := 100 ps;

-- timescale is 1ps

constant ONE_NS : time := 1 ns;

-- how many cycles to run

constant COUNT_PHASE : integer := 1024 + 1;

-- we'll be using the period in many locations

constant PER1 : time := 31.250 ns;

-- Declare the input clock signals

signal CLK_IN1 : std_logic := '1';

-- The high bit of the sampling counter

signal COUNT : std_logic;

-- Status and control signals

signal RESET : std_logic := '0';

signal LOCKED : std_logic;

signal COUNTER_RESET : std_logic := '0';

signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');

-- signal defined to stop mti simulation without severity failure in the report

signal end_of_sim : std_logic := '0';

signal CLK_OUT : std_logic_vector(1 downto 1);

--Freq Check using the M & D values setting and actual Frequency generated

component pll_ntsc_exdes

port

(-- Clock in ports

CLK_IN1 : in std_logic;

-- Reset that only drives logic in example design

COUNTER_RESET : in std_logic;

CLK_OUT : out std_logic_vector(1 downto 1) ;

-- High bits of counters driven by clocks

COUNT : out std_logic;

-- Status and control signals

RESET : in std_logic;

LOCKED : out std_logic

);

end component;

begin

-- Input clock generation

--------------------------------------

process begin

CLK_IN1 <= not CLK_IN1; wait for (PER1/2);

end process;

-- Test sequence

process

procedure simtimeprint is

variable outline : line;

begin

write(outline, string'("## SYSTEM_CYCLE_COUNTER "));

write(outline, NOW/PER1);

write(outline, string'(" ns"));

writeline(output,outline);

end simtimeprint;

procedure simfreqprint (period : time; clk_num : integer) is

variable outputline : LINE;

variable str1 : string(1 to 16);

variable str2 : integer;

variable str3 : string(1 to 2);

variable str4 : integer;

variable str5 : string(1 to 4);

begin

str1 := "Freq of CLK_OUT(";

str2 := clk_num;

str3 := ") ";

str4 := 1000000 ps/period ;

str5 := " MHz" ;

write(outputline, str1 );

write(outputline, str2);

write(outputline, str3);

write(outputline, str4);

write(outputline, str5);

writeline(output, outputline);

end simfreqprint;

begin

report "Timing checks are not valid" severity note;

RESET <= '1';

wait for (PER1*6);

RESET <= '0';

wait until LOCKED = '1';

wait for (PER1*20);

COUNTER_RESET <= '1';

wait for (PER1*19.5);

COUNTER_RESET <= '0';

wait for (PER1*1);

report "Timing checks are valid" severity note;

wait for (PER1*COUNT_PHASE);

simtimeprint;

end_of_sim <= '1';

wait for 1 ps;

report "Simulation Stopped." severity failure;

wait;

end process;

process (CLK_IN1)

procedure simtimeprint is

variable outline : line;

begin

write(outline, string'("## SYSTEM_CYCLE_COUNTER "));

write(outline, NOW/PER1);

write(outline, string'(" ns"));

writeline(output,outline);

end simtimeprint;

begin

if (CLK_IN1'event and CLK_IN1='1') then

timeout_counter <= timeout_counter + '1';

if (timeout_counter = "10000000000000") then

if (LOCKED /= '1') then

simtimeprint;

report "NO LOCK signal" severity failure;

end if;

end if;

end if;

end process;

-- Instantiation of the example design containing the clock

-- network and sampling counters

-----------------------------------------------------------

dut : pll_ntsc_exdes

port map

(-- Clock in ports

CLK_IN1 => CLK_IN1,

-- Reset for logic in example design

COUNTER_RESET => COUNTER_RESET,

CLK_OUT => CLK_OUT,

-- High bits of the counters

COUNT => COUNT,

-- Status and control signals

RESET => RESET,

LOCKED => LOCKED);

-- Freq Check

end test;

# file: simulate_isim.sh

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# create the project

vhpcomp -work work ../../implement/results/routed.vhd

vhpcomp -work work pll_ntsc_tb.vhd

# compile the project

fuse work.pll_ntsc_tb -L secureip -L simprim -o pll_ntsc_isim.exe

# run the simulation script

./pll_ntsc_isim.exe -tclbatch simcmds.tcl -sdfmax /pll_ntsc_tb/dut=../../implement/results/routed.sdf

# run the simulation script

#./pll_ntsc_isim.exe -gui -tclbatch simcmds.tcl

#/bin/sh

# file: simulate_mti.sh

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# set up the working directory

set work work

vlib work

# compile all of the files

vcom -work work ../../implement/results/routed.vhd

vcom -work work pll_ntsc_tb.vhd

# run the simulation

vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprim -sdfmax pll_ntsc_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_ntsc_tb

gui_open_window Wave

#!/bin/sh

# file: simulate_ncsim.sh

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# set up the working directory

mkdir work

# compile all of the files

ncvhdl -v93 -work work ../../implement/results/routed.vhd

ncvhdl -v93 -work work pll_ntsc_tb.vhd

# elaborate and run the simulation

ncsdfc ../../implement/results/routed.sdf

ncelab -work work -access +wc -pulse_r 10 -nonotifier work.pll_ntsc_tb -sdf_cmd_file sdf_cmd_file

ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.pll_ntsc_tb

# file: wave.do

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

onerror {resume}

quietly WaveActivateNextPane {} 0

add wave -noupdate -divider {Input clocks}

add wave -noupdate /pll_ntsc_tb/clk_in1

add wave -noupdate -divider {Output clocks}

add wave -noupdate /pll_ntsc_tb/clk_in1

add wave -noupdate /pll_ntsc_tb/count

add wave -noupdate /pll_ntsc_tb/counter_reset

add wave -noupdate /pll_ntsc_tb/locked

add wave -noupdate /pll_ntsc_tb/reset

TreeUpdate [SetDefaultTree]

WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}

configure wave -namecolwidth 238

configure wave -valuecolwidth 107

configure wave -justifyvalue left

configure wave -signalnamewidth 0

configure wave -snapdistance 10

configure wave -datasetprefix 0

configure wave -rowmargin 4

configure wave -childrowmargin 2

configure wave -gridoffset 0

configure wave -gridperiod 1

configure wave -griddelta 40

configure wave -timeline 0

configure wave -timelineunits ps

update

#!/bin/sh

# file: simulate_vcs.sh

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# remove old files

rm -rf simv* csrc DVEfiles AN.DB

# compile all of the files

# Note that -sverilog is not strictly required- You can

# remove the -sverilog if you change the type of the

# localparam for the periods in the testbench file to

# [63:0] from time

vhdlan -xlrm ../../implement/results/routed.vhd \

pll_ntsc_tb.vhd

# prepare the simulation

vcs +vcs+lic+wait -xlrm -sdf max:pll_ntsc_exdes:../../implement/results/routed.sdf -debug pll_ntsc_tb.vhd ../../implement/results/routed.vhd

# run the simulation

./simv -xlrm -ucli -i ucli_commands.key

# launch the viewer

#dve -vpd vcdplus.vpd -session vcs_session.tcl

Version 4

SymbolType BLOCK

TEXT 32 32 LEFT 4 pll_ntsc

RECTANGLE Normal 32 32 576 1088

LINE Normal 0 80 32 80

PIN 0 80 LEFT 36

PINATTR PinName clk_in1

PINATTR Polarity IN

LINE Normal 0 432 32 432

PIN 0 432 LEFT 36

PINATTR PinName reset

PINATTR Polarity IN

LINE Normal 608 80 576 80

PIN 608 80 RIGHT 36

PINATTR PinName clk_out1

PINATTR Polarity OUT

LINE Normal 608 976 576 976

PIN 608 976 RIGHT 36

PINATTR PinName locked

PINATTR Polarity OUT

-- file: pll_ntsc.vhd

--

-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

--

-- This file contains confidential and proprietary information

-- of Xilinx, Inc. and is protected under U.S. and

-- international copyright and other intellectual property

-- laws.

--

-- DISCLAIMER

-- This disclaimer is not a license and does not grant any

-- rights to the materials distributed herewith. Except as

-- otherwise provided in a valid license issued to you by

-- Xilinx, and to the maximum extent permitted by applicable

-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

-- (2) Xilinx shall not be liable (whether in contract or tort,

-- including negligence, or under any other theory of

-- liability) for any loss or damage of any kind or nature

-- related to, arising under or in connection with these

-- materials, including for any direct, or any indirect,

-- special, incidental, or consequential loss or damage

-- (including loss of data, profits, goodwill, or any type of

-- loss or damage suffered as a result of any action brought

-- by a third party) even if such damage or loss was

-- reasonably foreseeable or Xilinx had been advised of the

-- possibility of the same.

--

-- CRITICAL APPLICATIONS

-- Xilinx products are not designed or intended to be fail-

-- safe, or for use in any application requiring fail-safe

-- performance, such as life-support or safety devices or

-- systems, Class III medical devices, nuclear facilities,

-- applications related to the deployment of airbags, or any

-- other applications that could lead to death, personal

-- injury, or severe property or environmental damage

-- (individually and collectively, "Critical

-- Applications"). Customer assumes the sole risk and

-- liability of any use of Xilinx products in Critical

-- Applications, subject only to applicable laws and

-- regulations governing limitations on product liability.

--

-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

-- PART OF THIS FILE AT ALL TIMES.

--

------------------------------------------------------------------------------

-- User entered comments

------------------------------------------------------------------------------

-- None

--

------------------------------------------------------------------------------

-- "Output Output Phase Duty Pk-to-Pk Phase"

-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"

------------------------------------------------------------------------------

-- CLK_OUT1____57.143______0.000______50.0______290.503____196.077

--

------------------------------------------------------------------------------

-- "Input Clock Freq (MHz) Input Jitter (UI)"

------------------------------------------------------------------------------

-- __primary______________32____________0.010

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

library unisim;

use unisim.vcomponents.all;

entity pll_ntsc is

port

(-- Clock in ports

CLK_IN1 : in std_logic;

-- Clock out ports

CLK_OUT1 : out std_logic;

-- Status and control signals

RESET : in std_logic;

LOCKED : out std_logic

);

end pll_ntsc;

architecture xilinx of pll_ntsc is

attribute CORE_GENERATION_INFO : string;

attribute CORE_GENERATION_INFO of xilinx : architecture is "pll_ntsc,clk_wiz_v3_6,{component_name=pll_ntsc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=1,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";

-- Input clock buffering / unused connectors

signal clkin1 : std_logic;

-- Output clock buffering / unused connectors

signal clkfbout : std_logic;

signal clkfbout_buf : std_logic;

signal clkout0 : std_logic;

signal clkout1_unused : std_logic;

signal clkout2_unused : std_logic;

signal clkout3_unused : std_logic;

signal clkout4_unused : std_logic;

signal clkout5_unused : std_logic;

-- Unused status signals

begin

-- Input buffering

--------------------------------------

clkin1_buf : IBUFG

port map

(O => clkin1,

I => CLK_IN1);

-- Clocking primitive

--------------------------------------

-- Instantiation of the PLL primitive

-- * Unused inputs are tied off

-- * Unused outputs are labeled unused

pll_base_inst : PLL_BASE

generic map

(BANDWIDTH => "OPTIMIZED",

CLK_FEEDBACK => "CLKFBOUT",

COMPENSATION => "SYSTEM_SYNCHRONOUS",

DIVCLK_DIVIDE => 1,

CLKFBOUT_MULT => 25,

CLKFBOUT_PHASE => 0.000,

CLKOUT0_DIVIDE => 14,

CLKOUT0_PHASE => 0.000,

CLKOUT0_DUTY_CYCLE => 0.500,

CLKIN_PERIOD => 31.250,

REF_JITTER => 0.010)

port map

-- Output clocks

(CLKFBOUT => clkfbout,

CLKOUT0 => clkout0,

CLKOUT1 => clkout1_unused,

CLKOUT2 => clkout2_unused,

CLKOUT3 => clkout3_unused,

CLKOUT4 => clkout4_unused,

CLKOUT5 => clkout5_unused,

-- Status and control signals

LOCKED => LOCKED,

RST => RESET,

-- Input clock control

CLKFBIN => clkfbout_buf,

CLKIN => clkin1);

-- Output buffering

-------------------------------------

clkf_buf : BUFG

port map

(O => clkfbout_buf,

I => clkfbout);

clkout1_buf : BUFG

port map

(O => CLK_OUT1,

I => clkout0);

end xilinx;

# file: pll_ntsc.ucf

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# Input clock periods. These duplicate the values entered for the

# input clocks. You can use these to time your system

#----------------------------------------------------------------

NET "CLK_IN1" TNM_NET = "CLK_IN1";

TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 31.250 ns HIGH 50% INPUT_JITTER 312.5ps;

# FALSE PATH constraints

PIN "RESET" TIG;

# file: pll_ntsc.xdc

#

# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.

#

# This file contains confidential and proprietary information

# of Xilinx, Inc. and is protected under U.S. and

# international copyright and other intellectual property

# laws.

#

# DISCLAIMER

# This disclaimer is not a license and does not grant any

# rights to the materials distributed herewith. Except as

# otherwise provided in a valid license issued to you by

# Xilinx, and to the maximum extent permitted by applicable

# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND

# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES

# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING

# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-

# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and

# (2) Xilinx shall not be liable (whether in contract or tort,

# including negligence, or under any other theory of

# liability) for any loss or damage of any kind or nature

# related to, arising under or in connection with these

# materials, including for any direct, or any indirect,

# special, incidental, or consequential loss or damage

# (including loss of data, profits, goodwill, or any type of

# loss or damage suffered as a result of any action brought

# by a third party) even if such damage or loss was

# reasonably foreseeable or Xilinx had been advised of the

# possibility of the same.

#

# CRITICAL APPLICATIONS

# Xilinx products are not designed or intended to be fail-

# safe, or for use in any application requiring fail-safe

# performance, such as life-support or safety devices or

# systems, Class III medical devices, nuclear facilities,

# applications related to the deployment of airbags, or any

# other applications that could lead to death, personal

# injury, or severe property or environmental damage

# (individually and collectively, "Critical

# Applications"). Customer assumes the sole risk and

# liability of any use of Xilinx products in Critical

# Applications, subject only to applicable laws and

# regulations governing limitations on product liability.

#

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS

# PART OF THIS FILE AT ALL TIMES.

#

# Input clock periods. These duplicate the values entered for the

# input clocks. You can use these to time your system