Project

General

Profile

« Previous | Next » 

Revision 328

Added by markw over 10 years ago

sram works, boots, keyboard works

View differences:

papilioduo/atari800core_papilioduo.vhd
TV : integer := 1; -- 1 = PAL, 0=NTSC
SCANDOUBLE : integer := 0; -- 1 = YES, 0=NO, (+ later scanlines etc)
internal_rom : integer := 1 ;
internal_ram : integer := 8192;
--internal_ram : integer := 16384;
internal_ram : integer := 0;
ext_clock : integer := 0
);
PORT
......
signal PS2_KEYS : STD_LOGIC_VECTOR(511 downto 0);
signal PS2_KEYS_NEXT : STD_LOGIC_VECTOR(511 downto 0);
-- sram
signal ram_request : std_logic;
signal ram_request_complete : std_logic;
signal ram_read_enable : std_logic;
signal ram_write_enable : std_logic;
signal ram_addr : std_logic_vector(22 downto 0);
signal ram_do : std_logic_vector(31 downto 0);
signal ram_di : std_logic_vector(31 downto 0);
BEGIN
ARDUINO_RESET <= '0'; -- hold arduino in reset for now
SRAM_DATA <= (others => 'Z');
SRAM_ADDR <= (others => '0');
SRAM_CE <= '1';
SRAM_WE <= '1';
SRAM_OE <= '1';
LED1 <= '1';
LED2 <= '0';
LED3 <= '1';
LED4 <= '0';
u_DAC_L : entity work.dac
port map (
CLK_I => CLK,
......
atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
GENERIC MAP
(
cycle_length => 16,
cycle_length => 32,
internal_rom => internal_rom,
internal_ram => internal_ram,
video_bits => 8,
......
CONSOL_START => CONSOL_START,
-- TODO, connect to SRAM! Handle 32-bit in multiple cycles. How fast is the sram.
SDRAM_REQUEST => open,
SDRAM_REQUEST_COMPLETE => '1',
SDRAM_READ_ENABLE => open,
SDRAM_WRITE_ENABLE => open,
SDRAM_ADDR => open,
SDRAM_DO => (others=>'0'),
SDRAM_DI => open,
SDRAM_REQUEST => ram_request,
SDRAM_REQUEST_COMPLETE => ram_request_complete,
SDRAM_READ_ENABLE => ram_read_enable,
SDRAM_WRITE_ENABLE => ram_write_enable,
SDRAM_ADDR => ram_addr,
SDRAM_DO => ram_do,
SDRAM_DI => ram_di,
SDRAM_32BIT_WRITE_ENABLE => open,
SDRAM_16BIT_WRITE_ENABLE => open,
SDRAM_8BIT_WRITE_ENABLE => open,
......
generic map (COUNT=>32) -- cycle_length
port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
ram : entity work.sram
PORT MAP
(
ADDRESS => ram_addr(20 downto 0),
DIN => ram_di(7 downto 0),
WREN => ram_write_enable,
clk => clk,
reset_n => reset_n,
request => ram_request,
-- SRAM interface
SRAM_ADDR => sram_addr,
SRAM_CE_N => sram_ce,
SRAM_OE_N => sram_oe,
SRAM_WE_N => sram_we,
SRAM_DQ => sram_data,
-- Provide data to system
DOUT => ram_do(7 downto 0),
complete => ram_request_complete
);
ram_do(31 downto 8) <= (others=>'0');
END vhdl;
papilioduo/build.sh
xst -intstyle ise -ifn $name.xst -ofn $name.syr
echo "Starting NGD"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 $name.ngc $name.ngd
ngdbuild -intstyle ise -uc $name.ucf -dd _ngo -nt timestamp -p xc6slx9-tqg144-3 $name.ngc $name.ngd
echo "Starting Map..."
map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -detail -ir off -pr off -lc off -power off -o $name_map.ncd $name.ngd $name.pcf
papilioduo/papilioduo.ucf
CONFIG PROHIBIT=P60;
NET CLK_32 LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLK
NET RX LOC="P46" | IOSTANDARD=LVTTL; # RX
NET TX LOC="P141" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # TX
#NET RX LOC="P46" | IOSTANDARD=LVTTL; # RX
#NET TX LOC="P141" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # TX
NET ARDUINO_RESET LOC="P139" | IOSTANDARD=LVTTL; # ARDUINO_RESET
NET RS232_RX LOC="P116" | IOSTANDARD=LVTTL; # A0
NET RS232_TX LOC="P117" | IOSTANDARD=LVTTL; # A1
#NET RS232_RX LOC="P116" | IOSTANDARD=LVTTL; # A0
#NET RS232_TX LOC="P117" | IOSTANDARD=LVTTL; # A1
NET SD_MISO LOC="P118" | IOSTANDARD=LVTTL; # A2
NET SD_CD LOC="P119" | IOSTANDARD=LVTTL; # A3
NET PS2_DAT1 LOC="P120" | IOSTANDARD=LVTTL; # A4
......
NET SD_MOSI LOC="P115" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B0
NET SD_SCK LOC="P114" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B1
NET SD_nCS LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B2
NET SW_LEFT LOC="P111" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3
NET SW_UP LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B4
#NET SW_LEFT LOC="P111" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B3
#NET SW_UP LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B4
NET RESET LOC="P102" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B5
NET SW_DOWN LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B6
NET SW_RIGHT LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B7
#NET SW_DOWN LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B6
#NET SW_RIGHT LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # B7
NET VGA_HSYNC LOC="P99" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C0
NET VGA_VSYNC LOC="P97" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C1
NET VGA_BLUE(0) LOC="P93" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # C2
......
NET JOYSTICK2_6 LOC="P82" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D5
NET JOYSTICK2_7 LOC="P80" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D6
NET JOYSTICK2_9 LOC="P78" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D7
NET PS2_CLK2 LOC="P74" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D8
NET PS2_DAT2 LOC="P66" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D9
NET AUDIO2_RIGHT LOC="P61" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D10
NET AUDIO2_LEFT LOC="P58" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D11
#NET PS2_CLK2 LOC="P74" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D8
#NET PS2_DAT2 LOC="P66" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D9
#NET AUDIO2_RIGHT LOC="P61" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D10
#NET AUDIO2_LEFT LOC="P58" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D11
NET LED1 LOC="P56" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D12
NET LED2 LOC="P51" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D13
NET LED3 LOC="P48" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # D14
......
NET SRAM_CE LOC="P12" | IOSTANDARD=LVTTL; # SRAM_CE
NET SRAM_WE LOC="P6" | IOSTANDARD=LVTTL; # SRAM_WE
NET SRAM_OE LOC="P26" | IOSTANDARD=LVTTL; # SRAM_OE
NET JTAG_TMS LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS
NET JTAG_TCK LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK
NET JTAG_TDI LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI
NET JTAG_TDO LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO
NET FLASH_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS
NET FLASH_CK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK
NET FLASH_SI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI
NET FLASH_SO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO
#NET JTAG_TMS LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TMS
#NET JTAG_TCK LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TCK
#NET JTAG_TDI LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDI
#NET JTAG_TDO LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # JTAG_TDO
#NET FLASH_CS LOC="P38" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CS
#NET FLASH_CK LOC="P70" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_CK
#NET FLASH_SI LOC="P64" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST; # FLASH_SI
#NET FLASH_SO LOC="P65" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO
papilioduo/sram.vhdl
ENTITY sram IS
PORT
(
ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
ADDRESS : IN STD_LOGIC_VECTOR(20 DOWNTO 0);
DIN : IN STD_LOGIC_vector(7 downto 0);
WREN : IN STD_LOGIC;
......
request : in std_logic;
-- SRAM interface
SRAM_ADDR: OUT STD_LOGIC_VECTOR(17 downto 0);
SRAM_ADDR: OUT STD_LOGIC_VECTOR(20 downto 0);
SRAM_CE_N: OUT STD_LOGIC;
SRAM_OE_N: OUT STD_LOGIC;
SRAM_WE_N: OUT STD_LOGIC;
SRAM_LB_N: OUT STD_LOGIC;
SRAM_UB_N: OUT STD_LOGIC;
SRAM_DQ: INOUT STD_LOGIC_VECTOR(7 downto 0);
-- Provide data to system
DOUT : OUT STD_LOGIC_VECTOR(15 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(7 downto 0);
complete : out std_logic
);

Also available in: Unified diff