Revision 433
Added by markw almost 10 years ago
| replay/Replay.prj | ||
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Replay_Pack.vhd
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Replay_VideoTiming_Pack.vhd
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Replay_DDRCtrl_Pack.vhd
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Replay_TranslatePS2_Pack.vhd
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Replay_TranslatePS2.vhd
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FIFO_Async_D16.vhd
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FIFO_Async_D32.vhd
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FIFO_SyncSRL_D16.vhd
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FIFO_SyncBlock_D1024_W18.vhd
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FIFO_SyncBlock_D2048_W8.vhd
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DPRAM_BE_D64.vhd
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Replay_DDRCtrl_Datapath.vhd
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Replay_DDRCtrl.vhd
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Replay_DDRCtrl_Top.vhd
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replay_pack.vhd
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replay_videotiming_pack.vhd
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replay_ddrctrl_pack.vhd
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replay_translate_ps2_pack.vhd
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replay_translate_ps2.vhd
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fifo_async_d16.vhd
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fifo_async_d32.vhd
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fifo_syncsrl_d16.vhd
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fifo_syncblock_d1024_w18.vhd
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fifo_syncblock_d2048_w8.vhd
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dpram_be_d64.vhd
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replay_ddrctrl_datapath.vhd
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replay_ddrctrl.vhd
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replay_ddrctrl_top.vhd
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font0_rom.vhd
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font1_rom.vhd
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font2_rom.vhd
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kcpsm3.vhd
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ps2_rom.vhd
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Replay_I2C.vhd
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Replay_SPI8.vhd
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Replay_VideoTiming.vhd
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Replay_VideoConverter.vhd
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Replay_OSD.vhd
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Replay_Syscon.vhd
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Replay_FileIO_Sync.vhd
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Replay_Video.vhd
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Replay_ClockGen_Sync.vhd
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Replay_DDRCtrl.vhd
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Replay_JoyPS2.vhd
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Replay_Audio.vhd
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Replay_MousePointer.vhd
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replay_i2c.vhd
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replay_spi8.vhd
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replay_videotiming.vhd
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replay_videoconverter.vhd
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replay_osd.vhd
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replay_syscon.vhd
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replay_fileio_sync.vhd
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replay_video.vhd
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replay_clockgen_sync.vhd
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replay_ddrctrl.vhd
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replay_joy_ps2.vhd
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replay_audio.vhd
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replay_mousepointer.vhd
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cart_logic.vhd
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freezer_logic.vhd
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address_decoder.vhdl
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| replay/Replay.ucf | ||
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# Retro Gaming Platform
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# No Emulation No Compromise
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#
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# $Id: Replay.ucf 36 2013-09-08 17:32:44Z wolfgang.scherr $
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#
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# All rights reserved
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# Mike Johnson 2010
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CONFIG PART = XC3S1600E-FG320-4 ;
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NET ClK_A TNM_NET = clk_a_grp;
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NET ClK_B TNM_NET = clk_b_grp;
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NET ClK_C TNM_NET = clk_c_grp;
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NET i_clk_a TNM_NET = clk_a_grp;
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NET i_clk_b TNM_NET = clk_b_grp;
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NET i_clk_c TNM_NET = clk_c_grp;
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TIMESPEC TS03 = PERIOD : clk_a_grp : 9.39 ; # 106,47 MHz
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TIMESPEC TS02 = PERIOD : clk_b_grp : 20.13 ; # 49,66 MHz
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TIMESPEC TS01 = PERIOD : clk_c_grp : 36.98 ; # 27,04 MHz
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#TIMESPEC TS03 = PERIOD : clk_a_grp : 7.9 ; #typ
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#TIMESPEC TS02 = PERIOD : clk_b_grp : 20.1 ; #typ
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#TIMESPEC TS01 = PERIOD : clk_c_grp : 36.9 ; #typ
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TIMESPEC TS03 = PERIOD : clk_a_grp : 7.5 ; #w.c. (-5%)
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TIMESPEC TS02 = PERIOD : clk_b_grp : 19.1 ; #w.c. (-5%)
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TIMESPEC TS01 = PERIOD : clk_c_grp : 35.0 ; #w.c. (-5%)
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TIMESPEC TS11 = FROM:PADS:TO:FFS : 30 ns;
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TIMESPEC TS12 = FROM:FFS:TO:PADS : 30 ns;
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TIMESPEC TS11=FROM:PADS:TO:FFS : 30 ns;
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TIMESPEC TS12=FROM:FFS:TO:PADS : 30 ns;
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INST "u_ClockGen/u_a_dcm" LOC = "DCM_X2Y0";
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INST "u_ClockGen/phase_ctrl.u_a2_dcm" LOC = "DCM_X1Y0";
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| ... | ... | |
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#clock phase delay not important, between the two A dcms it does matter - force local routing
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# better result than one direct and one not
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NET "ClK_A" CLOCK_DEDICATED_ROUTE = FALSE;
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##PIN "u_ClockGen/u_a_dcm.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "i_clk_a" CLOCK_DEDICATED_ROUTE = FALSE;
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PIN "u_ClockGen/u_a_dcm.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
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PIN "u_ClockGen/phase_ctrl.u_a2_dcm" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "u_ClockGen/clk_a_ibuf" MAXSKEW = 0.3 ns;
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| ... | ... | |
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INST "u_ClockGen/phase_ctrl.u_dcm_a2_clk_bufg" LOC = "BUFGMUX_X2Y0";
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# C is routed to reset generator, phase not important
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NET "ClK_C" CLOCK_DEDICATED_ROUTE = FALSE;
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##PIN "u_ClockGen/u_c_dcm.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "i_clk_c" CLOCK_DEDICATED_ROUTE = FALSE;
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PIN "u_ClockGen/u_c_dcm.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
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INST "u_ClockGen/u_dcm_c_clk_0_bufg" LOC = "BUFGMUX_X2Y10";
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INST "u_ClockGen/u_dcm_c_clk_90_bufg" LOC = "BUFGMUX_X2Y11";
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INST "u_spi_bufg" LOC = "BUFGMUX_X1Y11";
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# 30MHz SPI clock MAX
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NET "i_FPGA_SPI_Clk" TNM_NET = i_FPGA_SPI_Clk;
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TIMESPEC TS_i_FPGA_SPI_Clk = PERIOD "i_FPGA_SPI_Clk" 30 ns HIGH 50%;
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NET "i_fpga_spi_clk" TNM_NET = spi_clk;
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TIMESPEC TS_I_FPGA_SPI_CLK = PERIOD "spi_clk" 20 ns HIGH 50%;
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# domain crossing
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NET Clk_Ram TNM_NET = clk_ram_grp;
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NET Clk_Capture TNM_NET = clk_capture_grp;
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NET Clk_Ctl TNM_NET = clk_ctl_grp;
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NET clk_ram TNM_NET = clk_ram_grp;
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NET clk_capture TNM_NET = clk_capture_grp;
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NET clk_ctl TNM_NET = clk_ctl_grp;
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TIMESPEC TS_20 = FROM "clk_ctl_grp" TO "clk_capture_grp" TIG;
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# warning that it is ignored, so commented out
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#TIMESPEC TS_20 = FROM "clk_ctl_grp" TO "clk_capture_grp" TIG;
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TIMESPEC TS_21 = FROM "clk_ram_grp" TO "clk_capture_grp" TIG;
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TIMESPEC TS_22 = FROM "clk_capture_grp" TO "clk_ram_grp" TIG;
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| ... | ... | |
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INST "u_ClockGen/u_reset" AREA_GROUP = "AG_u_ClockGen/u_reset" ;
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AREA_GROUP "AG_u_ClockGen/u_reset" RANGE = SLICE_X50Y143:SLICE_X55Y138 ;
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#INST "u_spi_input_mux" LOC = "SLICE_X47Y151";
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#
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# 3V3
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#
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NET "i_RS232_RXD" LOC = "A3" | IOSTANDARD = LVTTL;
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NET "b_Aux_IO(37)" LOC = "C3" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "o_RS232_RTS" LOC = "A4" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(0)" LOC = "B4" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(2)" LOC = "C4" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_RS232_CTS" LOC = "A5" | IOSTANDARD = LVTTL;
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NET "i_Joy_A(5)" LOC = "B5" | IOSTANDARD = LVTTL | PULLUP;
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NET "o_RS232_TXD" LOC = "C5" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_rs232_rxd" LOC = "A3" | IOSTANDARD = LVTTL;
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NET "b_aux_io(37)" LOC = "C3" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "o_rs232_rts" LOC = "A4" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(0)" LOC = "B4" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(2)" LOC = "C4" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_rs232_cts" LOC = "A5" | IOSTANDARD = LVTTL;
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NET "i_joy_a(5)" LOC = "B5" | IOSTANDARD = LVTTL | PULLUP;
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NET "o_rs232_txd" LOC = "C5" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(4)" LOC = "C2" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(5)" LOC = "D5" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(6)" LOC = "D6" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(7)" LOC = "E6" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(8)" LOC = "A11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(9)" LOC = "C7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(10)" LOC = "D7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(11)" LOC = "A14" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(12)" LOC = "E7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(13)" LOC = "A13" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(14)" LOC = "D9" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(15)" LOC = "G9" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(5)" LOC = "D5" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(26)" LOC = "A6" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(38)" LOC = "B6" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(6)" LOC = "D6" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(7)" LOC = "E6" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(29)" LOC = "A7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(9)" LOC = "C7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(10)" LOC = "D7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(26)" LOC = "A6" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(38)" LOC = "B6" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(29)" LOC = "A7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(12)" LOC = "E7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(3)" LOC = "F7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(27)" LOC = "A8" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_joy_b(0)" LOC = "B8" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_joy_a(4)" LOC = "C8" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_joy_a(1)" LOC = "D8" | IOSTANDARD = LVTTL | PULLUP;
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NET "b_fpga_spi_mosi" LOC = "E8" | IOSTANDARD = LVTTL;
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NET "b_aux_io(20)" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(3)" LOC = "F7" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(27)" LOC = "A8" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_Joy_B(0)" LOC = "B8" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_Joy_A(4)" LOC = "C8" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_Joy_A(1)" LOC = "D8" | IOSTANDARD = LVTTL | PULLUP;
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NET "b_FPGA_SPI_MOSI" LOC = "E8" | IOSTANDARD = LVTTL;
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NET "b_Aux_IO(20)" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_joy_a(2)" LOC = "B9" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_fpga_spi_clk" LOC = "C9" | IOSTANDARD = LVTTL;
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NET "b_aux_io(14)" LOC = "D9" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(25)" LOC = "E9" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_fpga_spi_miso" LOC = "F9" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(15)" LOC = "G9" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_Joy_A(2)" LOC = "B9" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_FPGA_SPI_Clk" LOC = "C9" | IOSTANDARD = LVTTL;
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NET "b_Aux_IO(25)" LOC = "E9" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_FPGA_SPI_MISO" LOC = "F9" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(32)" LOC = "A10" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_clk_b" LOC = "B10" | IOSTANDARD = LVTTL;
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NET "i_clk_c" LOC = "D10" | IOSTANDARD = LVTTL;
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NET "b_aux_io(17)" LOC = "E10" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_joy_b(3)" LOC = "F10" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_joy_b(5)" LOC = "G10" | IOSTANDARD = LVTTL | PULLUP;
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NET "b_aux_io(8)" LOC = "A11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(21)" LOC = "B11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(32)" LOC = "A10" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "ClK_B" LOC = "B10" | IOSTANDARD = LVTTL;
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NET "ClK_C" LOC = "D10" | IOSTANDARD = LVTTL;
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NET "b_Aux_IO(17)" LOC = "E10" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_Joy_B(3)" LOC = "F10" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_Joy_B(5)" LOC = "G10" | IOSTANDARD = LVTTL | PULLUP;
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NET "b_Aux_IO(21)" LOC = "B11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(23)" LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(22)" LOC = "D11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(34)" LOC = "E11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(36)" LOC = "F11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(24)" LOC = "A12" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_joy_a(0)" LOC = "C12" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_joy_b(2)" LOC = "D12" | IOSTANDARD = LVTTL | PULLUP;
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NET "b_aux_io(35)" LOC = "E12" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(23)" LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(22)" LOC = "D11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(34)" LOC = "E11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(36)" LOC = "F11" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(24)" LOC = "A12" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "i_Joy_A(0)" LOC = "C12" | IOSTANDARD = LVTTL | PULLUP;
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NET "i_Joy_B(2)" LOC = "D12" | IOSTANDARD = LVTTL | PULLUP;
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NET "b_Aux_IO(35)" LOC = "E12" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(30)" LOC = "F12" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(13)" LOC = "A13" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(28)" LOC = "B13" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(31)" LOC = "D13" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_ps2a_data" LOC = "E13" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(11)" LOC = "A14" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(16)" LOC = "B14" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_aux_io(33)" LOC = "C14" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(30)" LOC = "F12" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(28)" LOC = "B13" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_Aux_IO(31)" LOC = "D13" | IOSTANDARD = LVTTL | DRIVE = 8;
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NET "b_PS2A_Data" LOC = "E13" | IOSTANDARD = LVTTL | DRIVE = 8;
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||
|
NET "b_Aux_IO(16)" LOC = "B14" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_Aux_IO(33)" LOC = "C14" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_ps2a_clk" LOC = "D14" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_joy_a(3)" LOC = "A15" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_joy_b(1)" LOC = "B15" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_joy_b(4)" LOC = "C15" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_aux_io(18)" LOC = "A16" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_aux_io(19)" LOC = "B16" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "b_PS2A_Clk" LOC = "D14" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Joy_A(3)" LOC = "A15" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_Joy_B(1)" LOC = "B15" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_Joy_B(4)" LOC = "C15" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_Aux_IO(18)" LOC = "A16" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_Aux_IO(19)" LOC = "B16" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
#
|
||
|
# 2V5
|
||
|
#
|
||
|
#NET "" LOC = "B18"; # NC INP
|
||
|
NET "o_Mem_Addr(2)" LOC = "C18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_Addr(3)" LOC = "C17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(2)" LOC = "C18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(3)" LOC = "C17" | IOSTANDARD = SSTL2_I;
|
||
|
#NET "" LOC = "D18"; # VREF
|
||
|
NET "o_Disk_Led" LOC = "D17" | IOSTANDARD = LVCMOS25;
|
||
|
NET "o_Pwr_Led" LOC = "D16" | IOSTANDARD = LVCMOS25;
|
||
|
NET "o_disk_led" LOC = "D17" | IOSTANDARD = LVCMOS25;
|
||
|
NET "o_pwr_led" LOC = "D16" | IOSTANDARD = LVCMOS25;
|
||
|
#NET "" LOC = "E18"; # NC INP
|
||
|
#NET "" LOC = "E17"; # NC INP
|
||
|
|
||
|
NET "b_2V5_IO_1" LOC = "E16" | IOSTANDARD = LVCMOS25;
|
||
|
NET "b_2V5_IO_0" LOC = "E15" | IOSTANDARD = LVCMOS25;
|
||
|
NET "o_Mem_Addr(1)" LOC = "F18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_Addr(4)" LOC = "F17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_Addr(0)" LOC = "F15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_Addr(5)" LOC = "F14" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_2v5_io_1" LOC = "E16" | IOSTANDARD = LVCMOS25;
|
||
|
NET "b_2v5_io_0" LOC = "E15" | IOSTANDARD = LVCMOS25;
|
||
|
NET "o_mem_addr(1)" LOC = "F18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(4)" LOC = "F17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(0)" LOC = "F15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(5)" LOC = "F14" | IOSTANDARD = SSTL2_I;
|
||
|
#NET "" LOC = "G18"; # NC INP
|
||
|
NET "o_Mem_Addr(10)" LOC = "G16" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(10)" LOC = "G16" | IOSTANDARD = SSTL2_I;
|
||
|
|
||
|
NET "o_Mem_Addr(6)" LOC = "G15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_Addr(14)" LOC = "G14" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_Addr(7)" LOC = "G13" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(6)" LOC = "G15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(14)" LOC = "G14" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(7)" LOC = "G13" | IOSTANDARD = SSTL2_I;
|
||
|
#NET "" LOC = "H18"; # VREF
|
||
|
NET "o_Mem_Addr(13)" LOC = "H17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_Addr(8)" LOC = "H16" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_Addr(9)" LOC = "H15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_CS" LOC = "H14" | IOSTANDARD = SSTL2_I; # ctrl4
|
||
|
NET "o_mem_addr(13)" LOC = "H17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(8)" LOC = "H16" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_addr(9)" LOC = "H15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_cs" LOC = "H14" | IOSTANDARD = SSTL2_I; # ctrl4
|
||
|
|
||
|
#NET "" LOC = "H13"; # NC INP
|
||
|
NET "o_Mem_Addr(11)" LOC = "J17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_RAS" LOC = "J16" | IOSTANDARD = SSTL2_I; # ctrl3
|
||
|
NET "o_Mem_Addr(12)" LOC = "J15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_CAS" LOC = "J14" | IOSTANDARD = SSTL2_I; # ctrl2
|
||
|
NET "o_Mem_CKE" LOC = "J13" | IOSTANDARD = SSTL2_I; # ctrl0
|
||
|
NET "o_Mem_WE" LOC = "J12" | IOSTANDARD = SSTL2_I; # ctrl1
|
||
|
NET "o_mem_addr(11)" LOC = "J17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_ras" LOC = "J16" | IOSTANDARD = SSTL2_I; # ctrl3
|
||
|
NET "o_mem_addr(12)" LOC = "J15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_cas" LOC = "J14" | IOSTANDARD = SSTL2_I; # ctrl2
|
||
|
NET "o_mem_cke" LOC = "J13" | IOSTANDARD = SSTL2_I; # ctrl0
|
||
|
NET "o_mem_we" LOC = "J12" | IOSTANDARD = SSTL2_I; # ctrl1
|
||
|
|
||
|
#NET "" LOC = "K18"; # NC INP
|
||
|
#NET "" LOC = "K17"; # NC INP
|
||
|
NET "o_Mem_Clk_P" LOC = "K15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_Clk_N" LOC = "K14" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_Mem_UDM" LOC = "K13" | IOSTANDARD = SSTL2_I; # ctrl6
|
||
|
NET "o_Mem_LDM" LOC = "K12" | IOSTANDARD = SSTL2_I; # ctrl5
|
||
|
NET "b_Mem_UDQS" LOC = "L18" | IOSTANDARD = SSTL2_I; # ctrl8
|
||
|
NET "o_mem_clk_p" LOC = "K15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_clk_n" LOC = "K14" | IOSTANDARD = SSTL2_I;
|
||
|
NET "o_mem_udm" LOC = "K13" | IOSTANDARD = SSTL2_I; # ctrl6
|
||
|
NET "o_mem_ldm" LOC = "K12" | IOSTANDARD = SSTL2_I; # ctrl5
|
||
|
NET "b_mem_udqs" LOC = "L18" | IOSTANDARD = SSTL2_I; # ctrl8
|
||
|
#NET "" LOC = "L17"; # VREF
|
||
|
|
||
|
NET "b_Mem_DQ(8)" LOC = "L16" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(10)" LOC = "L15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(8)" LOC = "L16" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(10)" LOC = "L15" | IOSTANDARD = SSTL2_I;
|
||
|
#NET "" LOC = "L14"; # NC INP
|
||
|
#NET "" LOC = "L13"; # NC INP
|
||
|
NET "b_Mem_DQ(7)" LOC = "M18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(9)" LOC = "M16" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(6)" LOC = "M15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_LDQS" LOC = "M14" | IOSTANDARD = SSTL2_I; # ctrl7
|
||
|
NET "b_mem_dq(7)" LOC = "M18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(9)" LOC = "M16" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(6)" LOC = "M15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_ldqs" LOC = "M14" | IOSTANDARD = SSTL2_I; # ctrl7
|
||
|
|
||
|
#NET "" LOC = "M13" # VREF
|
||
|
NET "b_Mem_DQ(5)" LOC = "N18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(5)" LOC = "N18" | IOSTANDARD = SSTL2_I;
|
||
|
#NET "" LOC = "N17"; # NC INP
|
||
|
NET "b_Mem_DQ(4)" LOC = "N15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(11)" LOC = "N14" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(3)" LOC = "P18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(12)" LOC = "P17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(13)" LOC = "P16" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(4)" LOC = "N15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(11)" LOC = "N14" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(3)" LOC = "P18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(12)" LOC = "P17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(13)" LOC = "P16" | IOSTANDARD = SSTL2_I;
|
||
|
|
||
|
NET "i_Ext_Rst_L" LOC = "P15" | IOSTANDARD = LVCMOS25 | PULLUP;
|
||
|
NET "b_Mem_DQ(2)" LOC = "R18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "i_ext_rst_l" LOC = "P15" | IOSTANDARD = LVCMOS25 | PULLUP;
|
||
|
NET "b_mem_dq(2)" LOC = "R18" | IOSTANDARD = SSTL2_I;
|
||
|
#NET "" LOC = "R17"; # NC INP
|
||
|
#NET "" LOC = "R16"; # VREF
|
||
|
NET "b_Mem_DQ(14)" LOC = "R15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(1)" LOC = "T18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(0)" LOC = "T17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_Mem_DQ(15)" LOC = "U18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(14)" LOC = "R15" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(1)" LOC = "T18" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(0)" LOC = "T17" | IOSTANDARD = SSTL2_I;
|
||
|
NET "b_mem_dq(15)" LOC = "U18" | IOSTANDARD = SSTL2_I;
|
||
|
#
|
||
|
# 3V3
|
||
|
#
|
||
|
NET "i_Video_Int" LOC = "V16" | IOSTANDARD = LVTTL; #video15
|
||
|
NET "o_Audio_LRCIN" LOC = "T16" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Audio_MCLK" LOC = "V15" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Audio_BCKIN" LOC = "U15" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Audio_DIN" LOC = "T15" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_FPGA_Ctrl1" LOC = "V14" | IOSTANDARD = LVTTL;
|
||
|
NET "i_FPGA_Ctrl0" LOC = "U14" | IOSTANDARD = LVTTL;
|
||
|
NET "b_PS2B_Data" LOC = "T14" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_video_int" LOC = "V16" | IOSTANDARD = LVTTL; #video15
|
||
|
NET "o_audio_lrcin" LOC = "T16" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_audio_mclk" LOC = "V15" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_audio_bckin" LOC = "U15" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_audio_din" LOC = "T15" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_fpga_ctrl1" LOC = "V14" | IOSTANDARD = LVTTL;
|
||
|
NET "i_fpga_ctrl0" LOC = "U14" | IOSTANDARD = LVTTL;
|
||
|
NET "b_ps2b_data" LOC = "T14" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "b_PS2B_Clk" LOC = "R14" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Data(7)" LOC = "V13" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Data(0)" LOC = "U13" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Rst_L" LOC = "R13" | IOSTANDARD = LVTTL | DRIVE = 8; # video16
|
||
|
NET "o_Video_DE" LOC = "P13" | IOSTANDARD = LVTTL | DRIVE = 8; # video14
|
||
|
NET "o_Video_Data(2)" LOC = "V12" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Data(1)" LOC = "T12" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_V" LOC = "R12" | IOSTANDARD = LVTTL | DRIVE = 8; #video13
|
||
|
NET "b_ps2b_clk" LOC = "R14" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_data(7)" LOC = "V13" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_data(0)" LOC = "U13" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_rst_l" LOC = "R13" | IOSTANDARD = LVTTL | DRIVE = 8; # video16
|
||
|
NET "o_video_de" LOC = "P13" | IOSTANDARD = LVTTL | DRIVE = 8; # video14
|
||
|
NET "o_video_data(2)" LOC = "V12" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_data(1)" LOC = "T12" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_v" LOC = "R12" | IOSTANDARD = LVTTL | DRIVE = 8; #video13
|
||
|
|
||
|
NET "o_Video_H" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 8; #video12
|
||
|
NET "o_Video_Data(4)" LOC = "N12" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(0)" LOC = "U11" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_Aux_IP(6)" LOC = "T11" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "o_Video_Data(5)" LOC = "R11" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Data(3)" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Data(8)" LOC = "N11" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "ClK_A" LOC = "U10" | IOSTANDARD = LVTTL;
|
||
|
NET "o_video_h" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 8; #video12
|
||
|
NET "o_video_data(4)" LOC = "N12" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(0)" LOC = "U11" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_aux_ip(6)" LOC = "T11" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "o_video_data(5)" LOC = "R11" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_data(3)" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_data(8)" LOC = "N11" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_clk_a" LOC = "U10" | IOSTANDARD = LVTTL;
|
||
|
|
||
|
NET "b_SCL" LOC = "R10" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_SDA" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_scl" LOC = "R10" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_sda" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "o_Video_Clk_N" LOC = "V9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Clk_P" LOC = "U9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Data(9)" LOC = "R9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Data(6)" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_Clk_Aux" LOC = "N9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Clk_68K" LOC = "M9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(2)" LOC = "V8" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_Aux_IP(1)" LOC = "U8" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "o_video_clk_n" LOC = "V9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_clk_p" LOC = "U9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_data(9)" LOC = "R9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_data(6)" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_clk_aux" LOC = "N9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_clk_68k" LOC = "M9" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(2)" LOC = "V8" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_aux_ip(1)" LOC = "U8" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
|
||
|
NET "o_Video_Data(10)" LOC = "T8" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_Data(11)" LOC = "R8" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_HSync" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_Video_VSync" LOC = "N8" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_Video_DDC_Clk" LOC = "V7" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(4)" LOC = "T7" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_Aux_IP(3)" LOC = "R7" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_Video_DDC_Data" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_data(10)" LOC = "T8" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_data(11)" LOC = "R8" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_hsync" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "o_video_vsync" LOC = "N8" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_video_ddc_clk" LOC = "V7" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(4)" LOC = "T7" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_aux_ip(3)" LOC = "R7" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_video_ddc_data" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "b_IO(15)" LOC = "N7" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_Video_SPC" LOC = "V6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(0)" LOC = "U6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(1)" LOC = "R6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(2)" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(3)" LOC = "V5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(4)" LOC = "U5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(5)" LOC = "T5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(15)" LOC = "N7" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_video_spc" LOC = "V6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(0)" LOC = "U6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(1)" LOC = "R6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(2)" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(3)" LOC = "V5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(4)" LOC = "U5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(5)" LOC = "T5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "b_IO(6)" LOC = "R5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(5)" LOC = "V4" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(7)" LOC = "T4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(7)" LOC = "V3" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(8)" LOC = "U3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(8)" LOC = "V2" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(6)" LOC = "R5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(5)" LOC = "V4" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(7)" LOC = "T4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(7)" LOC = "V3" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(8)" LOC = "U3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(8)" LOC = "V2" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
#
|
||
|
# 3V3
|
||
|
#
|
||
|
NET "i_Aux_IP(9)" LOC = "U1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(9)" LOC = "T1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(10)" LOC = "T2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(10)" LOC = "R1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(11)" LOC = "R2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(12)" LOC = "R3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(11)" LOC = "R4" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(13)" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(9)" LOC = "U1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(9)" LOC = "T1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(10)" LOC = "T2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(10)" LOC = "R1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(11)" LOC = "R2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(12)" LOC = "R3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(11)" LOC = "R4" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(13)" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "b_IO(14)" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_Video_SPD" LOC = "P3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(43)" LOC = "P4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(12)" LOC = "N1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_Aux_IP(13)" LOC = "N2" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(42)" LOC = "N4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(41)" LOC = "N5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(14)" LOC = "M1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(14)" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_video_spd" LOC = "P3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(43)" LOC = "P4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(12)" LOC = "N1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_aux_ip(13)" LOC = "N2" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(42)" LOC = "N4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(41)" LOC = "N5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(14)" LOC = "M1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
|
||
|
NET "b_IO(40)" LOC = "M3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(27)" LOC = "M4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(26)" LOC = "M5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(25)" LOC = "M6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(24)" LOC = "L1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(23)" LOC = "L2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(22)" LOC = "L3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(21)" LOC = "L4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(40)" LOC = "M3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(27)" LOC = "M4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(26)" LOC = "M5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(25)" LOC = "M6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(24)" LOC = "L1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(23)" LOC = "L2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(22)" LOC = "L3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(21)" LOC = "L4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "b_IO(20)" LOC = "L5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(19)" LOC = "L6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(15)" LOC = "K2" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(18)" LOC = "K3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(17)" LOC = "K4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(16)" LOC = "K5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(44)" LOC = "K6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(16)" LOC = "K7" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(20)" LOC = "L5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(19)" LOC = "L6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(15)" LOC = "K2" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(18)" LOC = "K3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(17)" LOC = "K4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(16)" LOC = "K5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(44)" LOC = "K6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(16)" LOC = "K7" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
|
||
|
NET "b_IO(45)" LOC = "J1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(46)" LOC = "J2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(47)" LOC = "J4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(48)" LOC = "J5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(17)" LOC = "J6" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_Aux_IP(18)" LOC = "J7" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(49)" LOC = "H1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(50)" LOC = "H2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(45)" LOC = "J1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(46)" LOC = "J2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(47)" LOC = "J4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(48)" LOC = "J5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(17)" LOC = "J6" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_aux_ip(18)" LOC = "J7" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(49)" LOC = "H1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(50)" LOC = "H2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "b_IO(51)" LOC = "H3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(52)" LOC = "H4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(53)" LOC = "H5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(54)" LOC = "H6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(19)" LOC = "G1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(39)" LOC = "G3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(38)" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(37)" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(51)" LOC = "H3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(52)" LOC = "H4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(53)" LOC = "H5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(54)" LOC = "H6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(19)" LOC = "G1" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(39)" LOC = "G3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(38)" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(37)" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "b_IO(36)" LOC = "G6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(35)" LOC = "F1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(34)" LOC = "F2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(20)" LOC = "F4" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_Aux_IP(21)" LOC = "F5" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_IO(33)" LOC = "E1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(32)" LOC = "E2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(31)" LOC = "E3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(36)" LOC = "G6" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(35)" LOC = "F1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(34)" LOC = "F2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(20)" LOC = "F4" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "i_aux_ip(21)" LOC = "F5" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_io(33)" LOC = "E1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(32)" LOC = "E2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(31)" LOC = "E3" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
NET "b_IO(30)" LOC = "E4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(29)" LOC = "D1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_IO(28)" LOC = "D2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_Aux_IP(22)" LOC = "D3" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_Aux_IO(1)" LOC = "D4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_Aux_IO(39)" LOC = "C1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(30)" LOC = "E4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(29)" LOC = "D1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_io(28)" LOC = "D2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "i_aux_ip(22)" LOC = "D3" | IOSTANDARD = LVTTL | PULLUP;
|
||
|
NET "b_aux_io(1)" LOC = "D4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_aux_io(39)" LOC = "C1" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
NET "b_aux_io(4)" LOC = "C2" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
#NET "i_SSC_TF" LOC = "T3" | IOSTANDARD = LVTTL;
|
||
|
#NET "i_SSC_TD" LOC = "N10" | IOSTANDARD = LVTTL;
|
||
|
#NET "i_SSC_RK" LOC = "U16" | IOSTANDARD = LVTTL;
|
||
|
NET "o_SSC_RD" LOC = "U4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
#NET "i_ssc_tf" LOC = "T3" | IOSTANDARD = LVTTL;
|
||
|
#NET "i_ssc_td" LOC = "N10" | IOSTANDARD = LVTTL;
|
||
|
#NET "i_ssc_rk" LOC = "U16" | IOSTANDARD = LVTTL;
|
||
|
NET "o_ssc_rd" LOC = "U4" | IOSTANDARD = LVTTL | DRIVE = 8;
|
||
|
|
||
|
|
||
| replay/source/Core_Top.vhd | ||
|---|---|---|
|
use ieee.numeric_std.all;
|
||
|
use IEEE.STD_LOGIC_MISC.all;
|
||
|
|
||
|
use work.Replay_Pack.all;
|
||
|
use work.Replay_VideoTiming_Pack.all;
|
||
|
use work.Replay_TranslatePS2_Pack.all;
|
||
|
use work.replay_pack.all;
|
||
|
use work.replay_videotiming_pack.all;
|
||
|
use work.replay_translate_ps2_pack.all;
|
||
|
|
||
|
library UNISIM;
|
||
|
use UNISIM.Vcomponents.all;
|
||
| ... | ... | |
|
-- KEYBOARD MAPPER
|
||
|
----------------------------------------------------------
|
||
|
|
||
|
u_Kbd : entity work.Replay_TranslatePS2
|
||
|
u_kbd : entity work.replay_translate_ps2
|
||
|
generic map (
|
||
|
g_kb_map => c_800xl_kb_map
|
||
|
)
|
||
| ... | ... | |
|
core_hsyncn_s <= not(core_hsync);
|
||
|
core_vsyncn_s <= not(core_vsync);
|
||
|
|
||
|
vconv : entity work.Replay_VideoConverter
|
||
|
vconv : entity work.replay_videoconverter
|
||
|
generic map (
|
||
|
-- output format
|
||
|
g_Vid_Param_HD => c_Vidparam_720x576p_50,
|
||
| replay/source/Replay_Top.vhd | ||
|---|---|---|
|
use ieee.std_logic_unsigned.all;
|
||
|
use ieee.numeric_std.all;
|
||
|
|
||
|
use work.Replay_Pack.all;
|
||
|
use work.Replay_VideoTiming_Pack.all;
|
||
|
use work.replay_pack.all;
|
||
|
use work.replay_videotiming_pack.all;
|
||
|
|
||
|
library UNISIM;
|
||
|
use UNISIM.Vcomponents.all;
|
||
| ... | ... | |
|
entity Replay_Top is
|
||
|
port (
|
||
|
-- RS232 debug port
|
||
|
i_RS232_RXD : in bit1;
|
||
|
o_RS232_TXD : out bit1;
|
||
|
i_RS232_CTS : in bit1;
|
||
|
o_RS232_RTS : out bit1;
|
||
|
-- Joysticks
|
||
|
i_Joy_A : in word( 5 downto 0);
|
||
|
i_Joy_B : in word( 5 downto 0);
|
||
|
-- IO
|
||
|
b_IO : inout word(54 downto 0);
|
||
|
b_Aux_IO : inout word(39 downto 0);
|
||
|
i_rs232_rxd : in bit1;
|
||
|
o_rs232_txd : out bit1;
|
||
|
i_rs232_cts : in bit1;
|
||
|
o_rs232_rts : out bit1;
|
||
|
-- joysticks
|
||
|
i_joy_a : in word( 5 downto 0);
|
||
|
i_joy_b : in word( 5 downto 0);
|
||
|
-- io
|
||
|
b_io : inout word(54 downto 0);
|
||
|
b_aux_io : inout word(39 downto 0);
|
||
|
|
||
|
i_Aux_IP : in word(22 downto 0);
|
||
|
-- DRAM
|
||
|
o_Mem_Addr : out word(14 downto 0);
|
||
|
b_Mem_DQ : inout word(15 downto 0);
|
||
|
b_Mem_UDQS : inout bit1; -- Ctrl8
|
||
|
b_Mem_LDQS : inout bit1; -- Ctrl7
|
||
|
o_Mem_UDM : out bit1; -- Ctrl6
|
||
|
o_Mem_LDM : out bit1; -- Ctrl5
|
||
|
o_Mem_CS : out bit1; -- Ctrl4
|
||
|
o_Mem_RAS : out bit1; -- Ctrl3
|
||
|
o_Mem_CAS : out bit1; -- Ctrl2
|
||
|
o_Mem_WE : out bit1; -- Ctrl1
|
||
|
o_Mem_CKE : out bit1; -- Ctrl0
|
||
|
o_Mem_Clk_P : out bit1;
|
||
|
o_Mem_Clk_N : out bit1;
|
||
|
i_aux_ip : in word(22 downto 0);
|
||
|
-- dram
|
||
|
o_mem_addr : out word(14 downto 0);
|
||
|
b_mem_dq : inout word(15 downto 0);
|
||
|
b_mem_udqs : inout bit1; -- Ctrl8
|
||
|
b_mem_ldqs : inout bit1; -- Ctrl7
|
||
|
o_mem_udm : out bit1; -- Ctrl6
|
||
|
o_mem_ldm : out bit1; -- Ctrl5
|
||
|
o_mem_cs : out bit1; -- Ctrl4
|
||
|
o_mem_ras : out bit1; -- Ctrl3
|
||
|
o_mem_cas : out bit1; -- Ctrl2
|
||
|
o_mem_we : out bit1; -- Ctrl1
|
||
|
o_mem_cke : out bit1; -- Ctrl0
|
||
|
o_mem_clk_p : out bit1;
|
||
|
o_mem_clk_n : out bit1;
|
||
|
--
|
||
|
o_Disk_Led : out bit1;
|
||
|
o_Pwr_Led : out bit1;
|
||
|
o_disk_led : out bit1;
|
||
|
o_pwr_led : out bit1;
|
||
|
--
|
||
|
i_Ext_Rst_L : in bit1; -- pullup
|
||
|
b_2V5_IO_1 : inout bit1;
|
||
|
b_2V5_IO_0 : inout bit1;
|
||
|
-- Video
|
||
|
o_Video_Clk_P : out bit1;
|
||
|
o_Video_Clk_N : out bit1;
|
||
|
o_Video_Rst_L : out bit1; -- Video16
|
||
|
i_Video_Int : in bit1; -- Video15
|
||
|
o_Video_DE : out bit1; -- Video14
|
||
|
o_Video_V : out bit1; -- Video13
|
||
|
o_Video_H : out bit1; -- Video12
|
||
|
o_Video_Data : out word(11 downto 0); --Video11..0
|
||
|
b_Video_DDC_Clk : out bit1;
|
||
|
b_Video_DDC_Data : out bit1;
|
||
|
o_Video_HSync : out bit1;
|
||
|
o_Video_VSync : out bit1;
|
||
|
b_Video_SPC : inout bit1;
|
||
|
b_Video_SPD : inout bit1;
|
||
|
-- Audio
|
||
|
o_Audio_LRCIN : out bit1; -- Audio3
|
||
|
o_Audio_MCLK : out bit1; -- Audio2
|
||
|
o_Audio_BCKIN : out bit1; -- Audio1
|
||
|
o_Audio_DIN : out bit1; -- Audio0
|
||
|
i_ext_rst_l : in bit1; -- pullup
|
||
|
b_2v5_io_1 : inout bit1;
|
||
|
b_2v5_io_0 : inout bit1;
|
||
|
-- video
|
||
|
o_video_clk_p : out bit1;
|
||
|
o_video_clk_n : out bit1;
|
||
|
o_video_rst_l : out bit1; -- Video16
|
||
|
i_video_int : in bit1; -- Video15
|
||
|
o_video_de : out bit1; -- Video14
|
||
|
o_video_v : out bit1; -- Video13
|
||
|
o_video_h : out bit1; -- Video12
|
||
|
o_video_data : out word(11 downto 0); --Video11..0
|
||
|
b_video_ddc_clk : out bit1;
|
||
|
b_video_ddc_data : out bit1;
|
||
|
o_video_hsync : out bit1;
|
||
|
o_video_vsync : out bit1;
|
||
|
b_video_spc : inout bit1;
|
||
|
b_video_spd : inout bit1;
|
||
|
-- audio
|
||
|
o_audio_lrcin : out bit1; -- Audio3
|
||
|
o_audio_mclk : out bit1; -- Audio2
|
||
|
o_audio_bckin : out bit1; -- Audio1
|
||
|
o_audio_din : out bit1; -- Audio0
|
||
|
--
|
||
|
b_PS2A_Clk : inout bit1;
|
||
|
b_PS2A_Data : inout bit1;
|
||
|
b_PS2B_Clk : inout bit1;
|
||
|
b_PS2B_Data : inout bit1;
|
||
|
b_ps2a_clk : inout bit1;
|
||
|
b_ps2a_data : inout bit1;
|
||
|
b_ps2b_clk : inout bit1;
|
||
|
b_ps2b_data : inout bit1;
|
||
|
|
||
|
b_SCL : inout bit1;
|
||
|
b_SDA : inout bit1;
|
||
|
b_scl : inout bit1;
|
||
|
b_sda : inout bit1;
|
||
|
|
||
|
-- System control
|
||
|
i_FPGA_Ctrl0 : in bit1;
|
||
|
i_FPGA_Ctrl1 : in bit1;
|
||
|
i_FPGA_SPI_Clk : in bit1;
|
||
|
b_FPGA_SPI_MOSI : inout bit1;
|
||
|
b_FPGA_SPI_MISO : inout bit1;
|
||
|
-- system control
|
||
|
i_fpga_ctrl0 : in bit1;
|
||
|
i_fpga_ctrl1 : in bit1;
|
||
|
i_fpga_spi_clk : in bit1;
|
||
|
b_fpga_spi_mosi : inout bit1;
|
||
|
b_fpga_spi_miso : inout bit1;
|
||
|
|
||
|
-- SSC & config pins
|
||
|
--i_SSC_TF : in bit1; --io_init input during config
|
||
|
--i_SSC_TD : in bit1; --io_din input during config
|
||
|
--i_SSC_RK : in bit1; --io_cclk input during config
|
||
|
o_SSC_RD : out bit1; --io_dout output during config -- vertical sync for MCU (sync OSD update)
|
||
|
-- ssc & config pins
|
||
|
--i_ssc_tf : in bit1; --io_init input during config
|
||
|
--i_ssc_td : in bit1; --io_din input during config
|
||
|
--i_ssc_rk : in bit1; --io_cclk input during config
|
||
|
o_ssc_rd : out bit1; --io_dout output during config -- vertical sync for MCU (sync OSD update)
|
||
|
--
|
||
|
-- Clocks
|
||
|
-- clocks
|
||
|
--
|
||
|
o_Clk_68K : out bit1; -- source terminated to connector
|
||
|
b_Clk_Aux : inout bit1; -- direct to connector
|
||
|
ClK_A : in bit1;
|
||
|
ClK_B : in bit1;
|
||
|
ClK_C : in bit1
|
||
|
o_clk_68k : out bit1; -- source terminated to connector
|
||
|
b_clk_aux : inout bit1; -- direct to connector
|
||
|
i_clk_a : in bit1;
|
||
|
i_clk_b : in bit1;
|
||
|
i_clk_c : in bit1
|
||
|
|
||
|
);
|
||
|
end;
|
||
| ... | ... | |
|
begin
|
||
|
u_spi_bufg : BUFG port map (I => i_FPGA_SPI_Clk, O => clk_spi);
|
||
|
|
||
|
u_ClockGen : entity work.Replay_ClockGen
|
||
|
u_ClockGen : entity work.replay_clockgen
|
||
|
generic map (
|
||
|
G_DIVIDER => 11
|
||
|
)
|
||
|
port map (
|
||
|
i_ClK_A => Clk_A,
|
||
|
i_ClK_B => Clk_B,
|
||
|
i_ClK_C => Clk_C,
|
||
|
i_ClK_A => i_Clk_A,
|
||
|
i_ClK_B => i_Clk_B,
|
||
|
i_ClK_C => i_Clk_C,
|
||
|
--
|
||
|
i_Rst_L => i_Ext_Rst_L, -- hard reset
|
||
|
i_Rst_Soft => rst_soft, -- NOT DRAM!
|
||
| ... | ... | |
|
|
||
|
-- I/O
|
||
|
|
||
|
u_JoyPS2 : entity work.Replay_JoyPS2
|
||
|
u_joyps2 : entity work.replay_joy_ps2
|
||
|
port map (
|
||
|
i_Clk => clk_ctl,
|
||
|
i_Tick_1us => tick_ctl_1us,
|
||
| ... | ... | |
|
--
|
||
|
-- IO Joysticks
|
||
|
--
|
||
|
i_Joy_A => i_Joy_A,
|
||
|
i_Joy_B => i_Joy_B,
|
||
|
i_Joy_A_l => i_Joy_A,
|
||
|
i_Joy_B_l => i_Joy_B,
|
||
|
|
||
|
-- IO PS2
|
||
|
i_PS2A_Clk => b_PS2A_Clk,
|
||
| ... | ... | |
|
|
||
|
-- mch_ddr_valid <= mch_valid when (mch_addr(31) = '0') else '0'; -- first addresses from 0x00000000 on are DRAM, from 0x80000000 on is for other memory
|
||
|
|
||
|
u_DDRCtrl : entity work.Replay_DDRCtrl_top
|
||
|
u_ddrctrl : entity work.replay_ddrctrl_top
|
||
|
port map (
|
||
|
i_Clk_Ram => clk_ram,
|
||
|
i_Clk_Ram_90 => clk_ram_90,
|
||
| ... | ... | |
|
--
|
||
|
-- System control / On Screen Display
|
||
|
--
|
||
|
u_Syscon : entity work.Replay_Syscon
|
||
|
u_syscon : entity work.replay_syscon
|
||
|
generic map (
|
||
|
-- defaults
|
||
|
g_cfg_static => x"00000000",
|
||
| ... | ... | |
|
b_FPGA_SPI_MISO <= spi_fileio_miso when (spi_fileio_cs_l = '0') else 'Z';
|
||
|
b_FPGA_SPI_MISO <= spi_syscon_miso when (spi_syscon_cs_l = '0') else 'Z';
|
||
|
|
||
|
u_FileIO : entity work.Replay_FileIO
|
||
|
u_fileio : entity work.replay_fileio
|
||
|
port map (
|
||
|
-- handles all disk/tape/HDD/ROM transfers to the SD card/ARM
|
||
|
i_Clk_Ctl => clk_ctl,
|
||
| ... | ... | |
|
--
|
||
|
-- VIDEO
|
||
|
--
|
||
|
u_Video : entity work.Replay_Video
|
||
|
u_video : entity work.replay_video
|
||
|
port map (
|
||
|
i_Clk_Vid => clk_vid,
|
||
|
i_Clk_Vid_90 => clk_vid_90,
|
||
| ... | ... | |
|
--
|
||
|
-- AUDIO PHY
|
||
|
--
|
||
|
u_Audio : entity work.Replay_Audio
|
||
|
u_audio : entity work.replay_audio
|
||
|
port map (
|
||
|
i_Clk => clk_aud, --sys,
|
||
|
i_Ena => '1', --ena_sys,
|
||
Made replay build with latest replay svn - need to verify it works though - really need to do some work on this platform...