Revision 683
Added by markw over 7 years ago
| ultimate_cart/veronica/slave_timing_6502.vhd | ||
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end if;
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end if;
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when state_write_request =>
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if (delay_reg(45)='1') then -- n+4 cycles
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if (delay_reg(47)='1') then -- n+4 cycles
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bus_data_in_next <= bus_data;
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end if;
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if (delay_reg(46)='1') then -- n+4 cycles
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if (delay_reg(48)='1') then -- n+4 cycles
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internal_memory_request <= '1';
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state_next <= state_wait_addrctl;
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end if;
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Back off by 2 cycles, make it more reliable (was missing some eclairexl writes)