Revision 70
Added by markw over 11 years ago
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SPI_MISO: out std_logic;
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SPI_MOSI : in std_logic;
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-- Sector access request
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request : in std_logic;
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-- Sector access read_request
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read_request : in std_logic;
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write_request : in std_logic;
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sector : in std_logic_vector(23 downto 0);
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ready : out std_logic;
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| ... | ... | |
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signal cnt_next : std_logic_vector(15 downto 0);
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signal cnt_reg : std_logic_vector(15 downto 0);
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signal data_in_next : std_logic_vector(7 downto 0);
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signal data_in_reg : std_logic_vector(7 downto 0);
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signal data_out_next : std_logic_vector(7 downto 0);
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signal data_out_reg : std_logic_vector(7 downto 0);
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| ... | ... | |
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signal sector_next : std_logic_vector(23 downto 0);
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signal sector_reg : std_logic_vector(23 downto 0);
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signal request_next : std_logic;
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signal request_reg : std_logic;
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signal read_request_next : std_logic;
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signal read_request_reg : std_logic;
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signal write_request_next : std_logic;
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signal write_request_reg : std_logic;
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signal clk2 : std_logic;
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begin
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process(clk,reset_n)
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clk2 <= clk or spi_ss_io;
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process(clk2,reset_n,spi_ss_io)
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begin
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if (reset_n = '0') then
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if (spi_ss_io = '1') then
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cnt_reg <= (others=>'0');
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cmd_reg <= (others=>'0');
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wren_reg <= '0';
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elsif (reset_n = '0') then
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cnt_reg <= (others=>'0');
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cmd_reg <= (others=>'0');
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sbuf_reg <= (others=>'0');
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addr_reg <= (others => '0');
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data_in_reg <= (others => '0');
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data_out_reg <= (others => '0');
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wren_reg <= '0';
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| ... | ... | |
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transmit_reg <= (others=>'0');
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request_reg <= '0';
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read_request_reg <= '0';
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write_request_reg <= '0';
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sector_reg <=(others=>'0');
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elsif (clk'event and clk='1') then
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elsif (clk2'event and clk2='1') then
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cnt_reg <= cnt_next;
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cmd_reg <= cmd_next;
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sbuf_reg <= sbuf_next;
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addr_reg <= addr_next;
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data_in_reg <= data_in_next;
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data_out_reg <= data_out_next;
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wren_reg <= wren_next;
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| ... | ... | |
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transmit_reg <= transmit_next;
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request_reg <= request_next;
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read_request_reg <= read_request_next;
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write_request_reg <= write_request_next;
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sector_reg <= sector_next;
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end if;
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end process;
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| ... | ... | |
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-- select_sync : synchronizer
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-- PORT MAP ( CLK => clk, raw => spi_ss_io, sync=>spi_ss_next);
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data_in_next <= data_in;
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process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, request_reg, ready_reg,request,sector)
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process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, write_request_reg, read_request_reg, ready_reg,read_request,write_request,sector,data_in_reg)
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begin
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cnt_next <= cnt_reg;
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sbuf_next <= sbuf_reg;
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cmd_next <= cmd_reg;
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ready_next <= ready_reg and request; -- stay ready until request cleared (received by other end)
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ready_next <= ready_reg and (read_request or write_request); -- stay ready until read_request cleared (received by other end)
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transmit_next <= transmit_reg;
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| ... | ... | |
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addr_next <= addr_reg;
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sector_next <= sector_reg;
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request_next <= request_reg;
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read_request_next <= read_request_reg;
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write_request_next <= write_request_reg;
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--- It polls get_status 10 times a second
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--- it uses SPI_SS2 for this
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| ... | ... | |
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sbuf_next(6 downto 1) <= sbuf_reg(5 downto 0);
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sbuf_next(0) <= SPI_MOSI;
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if (cnt_reg = X"0000") then
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addr_next <= (others=>'0');
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end if;
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if (cnt_reg = X"0007") then
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cmd_next(7 downto 1) <= sbuf_reg;
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cmd_next(0) <= SPI_MOSI;
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addr_next <= (others=>'1');
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sector_next <= sector;
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request_next <= request;
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read_request_next <= read_request;
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write_request_next <= write_request;
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end if;
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--end if;
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if (spi_ss_io = '1') then
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cnt_next <= (others=>'0');
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cmd_next <= (others=>'0');
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end if;
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case cmd_reg is
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when X"50" => --get status
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case cnt_reg is
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| ... | ... | |
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when X"0018" =>
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transmit_next <= sector_reg(7 downto 0);
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when X"0020" =>
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transmit_next <= "1010010"&request_reg; --read request
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transmit_next <= "101001"&write_request_reg&read_request_reg; --read read_request
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when others =>
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-- nothing
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end case;
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when X"51" => --sector read from sd, write it...
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if (cnt_reg = X"0008") then
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addr_next <= (others=>'1');
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end if;
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if (cnt_reg(2 downto 0) = "111") then
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addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
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data_out_next(7 downto 1) <= sbuf_reg;
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data_out_next(0) <= SPI_MOSI;
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wren_next <= request;
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wren_next <= read_request;
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if (cnt_reg(12) = '1')then
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ready_next <= '1';
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end if;
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end if;
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when X"52" => -- read from write, write to sd
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if (cnt_reg(2 downto 0) = "000") then
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addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
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transmit_next <= data_in_reg;
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if (cnt_reg(12) = '1')then
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ready_next <= '1';
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end if;
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end if;
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when others =>
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-- nop
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end case;
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end process;
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-- outputs
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addr <= addr_reg;
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data_out <= data_out_reg;
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wr_en <= wren_reg;
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addr <= addr_next;
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data_out <= data_out_next;
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wr_en <= wren_next;
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ready <= ready_reg;
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Added ZPU. Added read/write SD support. Fixed joystick. Switched to new mist keyboard mode (ps2 emulation).