Project

General

Profile

Pinouts » History » Version 2

foft, 04/15/2018 07:24 PM

1 1 foft
h1. Pinouts
2 2 foft
h2. V1
3
h2. V2
4 1 foft
h3. Use in core
5
6
h3. By connection to FPGA
7
GPIO:
8
1-17: direct to FPGA
9
18: SDA (i2c) - clock gen also on here
10
19: SCL (i2c) - clock gen also on here
11
20-22: GND
12
23-34: 3.3V
13
25-26: 5.0V
14
15
Interface 1:
16
All level shifted to 3.3V.
17
Special pins:
18
37:RD4: 10k pulldown
19
40:RD5: 10k pulldown
20
34:MPD_N: 4.7k pullup to 5V
21
28:IRQ_N: 4.7k pullup to 5V
22
32:REF_N: 2k pullup to 5V
23
24
Interface 2:
25
1-3: USB to FTDI 
26
4: GND
27
5,6: 5V
28
7-10: Charge cap, FPGA compares with ref voltage
29
11-30: level shifted to 3.3V. 4.7k pullup to 5V. Direction pins have extra 220 ohm resistance (needed?)
30
31: GND
31
32-33: level shifted to 3.3V. 4.7k pullup to 5V
32
34: 5V transistor drive (for tape motor)
33
35-49: level shifted to 3.3V. 4.7k pullup o 5V
34
40: EXTSEL_N: level shifted to 3.3V. 4.7k pullup to 5V