Project

General

Profile

Pinouts » History » Version 3

foft, 04/15/2018 07:25 PM

1 1 foft
h1. Pinouts
2 3 foft
3 2 foft
h2. V1
4 3 foft
5 2 foft
h2. V2
6 3 foft
7 1 foft
h3. Use in core
8
9
h3. By connection to FPGA
10
GPIO:
11
1-17: direct to FPGA
12
18: SDA (i2c) - clock gen also on here
13
19: SCL (i2c) - clock gen also on here
14
20-22: GND
15
23-34: 3.3V
16
25-26: 5.0V
17
18
Interface 1:
19
All level shifted to 3.3V.
20
Special pins:
21
37:RD4: 10k pulldown
22
40:RD5: 10k pulldown
23
34:MPD_N: 4.7k pullup to 5V
24
28:IRQ_N: 4.7k pullup to 5V
25
32:REF_N: 2k pullup to 5V
26
27
Interface 2:
28
1-3: USB to FTDI 
29
4: GND
30
5,6: 5V
31
7-10: Charge cap, FPGA compares with ref voltage
32
11-30: level shifted to 3.3V. 4.7k pullup to 5V. Direction pins have extra 220 ohm resistance (needed?)
33
31: GND
34
32-33: level shifted to 3.3V. 4.7k pullup to 5V
35
34: 5V transistor drive (for tape motor)
36
35-49: level shifted to 3.3V. 4.7k pullup o 5V
37
40: EXTSEL_N: level shifted to 3.3V. 4.7k pullup to 5V