Bug #43
closedCore 10 - IDE2+ Menu does not show when powering the computer with START key pressed
0%
Description
the PBI device i am testing is the IDE2+ external interface that plugs to the PBI port
when i reset the computer with the START key pressed the IDE2+ menu should appear.
on a real atari it does but not on the ExlaireXL board
Files
Updated by foft over 7 years ago
Does the rest of it work, just not the menu?
Do you have a logic analyzer? I can outputs some signals on the gpio for debugging.
Do you have any technical documentation, schematics etc?
Updated by foft over 7 years ago
Perhaps we can test it by poking/peeking regs from basic...
Updated by ndary over 7 years ago
no, i dont have a logic analyzer or the schematics...
let me see what info i can gather
Updated by ndary over 7 years ago
i found this document.. can it be missing voltage on the PBI port?
the interface seems to work on the Eclair, when i press one of its buttons the LEDS respond.. but the menu will not boot
DOES ANYONE HERE HAVE THE BLACK BOX OR THE MIO INTERFACE to test?
Nir
Updated by sadosp over 7 years ago
Nir,
If you power on eclaireXL and go to Basic, after keep down the start key and simultaneously press and leave the F10, after the IDE2+ menu appears?
Updated by foft over 7 years ago
There is 5V on pin 47 and pin 48.
I see it drives EXSEL and MPD. I thought I'm handling that case properly, but I can check...
Updated by foft over 7 years ago
I checked MPD...
If MPD and EXTSEL are used in conjunction that seems to work fine.
If just MPD is used to expose the ram under the OS that does not work. I doubt it uses that, but I should still fix it.
Updated by foft over 7 years ago
Found an issue with RST_N. I had disconnected it in v10 (I forgot) because when I reset the freezer broke. Well I was just pulling it low for reset, then going high impedance for high. However there is no pull up on it! So I need to drive RST_N high...
I wonder if the IDE2+ needs rst_n.
Updated by foft over 7 years ago
- Related to Bug #44: CORE 11 - Bug in PBI - EclaireXL will not boot with IDE2+ Is connected and when Turbo Freezer connected goes directly to Cart EMU not main screen added
Updated by foft over 7 years ago
IDEPlus info from Simius:
IDE+ detaches OS ROM between $D800 and $DFFF and plug his own memory there. I uses also $D1xx page and $A000...$BFFF area for SDX
IDE+ uses all PBI signals, except: RAS, CAS, RDY, REF, EXTENB and AUDIO
IDE+ latches the address bus (always) about 80ns before rising edge of PHI2 and the data bus (during write cycles) about 80ns before falling edge.
Updated by Stephen over 7 years ago
ndary wrote:
i found this document.. can it be missing voltage on the PBI port?
the interface seems to work on the Eclair, when i press one of its buttons the LEDS respond.. but the menu will not boot
DOES ANYONE HERE HAVE THE BLACK BOX OR THE MIO INTERFACE to test?
Nir
Nir, I do have a 256kB MIO. Two issues. First I don't know if it works, as I don't believe I've ever even turned it on since I bought it. Second, I have no SCSI interface drives to test it with. Most I could hope to do is see if the menu comes up. I am trying to locate a SCSI drive.
Updated by foft over 7 years ago
- Related to Bug #45: CORE10 - IDE2+ SDX not working added
Updated by ndary over 7 years ago
can you confirm that you get to the MIO Menu?
Nir
Updated by Stephen over 7 years ago
ndary wrote:
can you confirm that you get to the MIO Menu?
Nir
After dinner I will find a power supply for the MIO. First I have to confirm it works on real hardware, and then yes, I will let you guys know if it works with CORE11 (or 10).
Updated by foft over 7 years ago
More info from Simus:
$D800..$DDFF is a ROM, $DE00...$DFFF is a RAM.
MPD is kept low all the time when apropriated bit in PDVREG ($D1FF) is set. EXTSEL is pulled down 40-50ns after one of two conditions occured:
1. MPD is low and address bus is $D800...$DFFF.
2. SDX is on and address bus is $A000...$BFFF
...and released 40-50ns after these conditions are terminated.
Latch signals are generated by HCT123A monostable multivibrator. Pulse width is set at 180ns and is triggered by falling (address) and rising (data) edge of PHI2. With a propagation delays it does ca. 200ns.
Updated by ndary over 7 years ago
Tested and working on Core 13, need other guys to test on MIO and BlackBox
Nir
Updated by foft almost 7 years ago
- Status changed from New to Closed
Marking as closed since the IDE2+ itself seems to work. Would be nice to test the black box and MIO but if someone does and finds an issue that than be raised elsewhere.