Activity

From 04/16/2017 to 05/15/2017

FO 09:52 PM Bug #17 (Closed): NTSC crashing on some builds: Investigate why... On the v1 core this occurred when running the PLL at very high fVCO. However we already fixed that in v1, so not sure why.
foft
FO 07:48 PM Bug #16 (Closed): Audio bug report for Altirra: One for the coders, please can you check if these bugs are present?
From post on atariage...
http://atariage.com/forums/topic/256683-altirra-280-released/page-24#entry3760704
Let me report a couple of issues with POKEY chip in Altir... foft

FO 09:42 PM Feature #15: Implement programmable PLL: Attaching PLL chip datasheet foft
FO 09:41 PM Feature #15 (New): Implement programmable PLL: See if the programmable PLL works. This will allow us to support different/custom VGA modes, once we have EDID/DDC working. For now I just want to find out if its alive. foft
FO 08:38 PM Feature #13: 32x speed cpu without wait states: So thinking about options...
Double the main clock speed and pipeline a bit
or
Output next address from antic and the cpu, so I can read the memory 1 cycle earlier - antic clearly knows what it will read, does the 6502 core?
or
A... foft
FO 08:34 PM Feature #7: Implement I2C vga/hdmi support: Used this controller for the ADC on v1: https://eewiki.net/pages/viewpage.action?pageId=10125324
So I guess I just need to wire this to the ZPU, then I can experiment with this in firmware.
I guess a write FIFO that captures 16 bits ... foft
FO 08:30 PM Feature #7: Implement I2C vga/hdmi support: DDC looks a little funkier foft
FO 08:28 PM Feature #7: Implement I2C vga/hdmi support: EDID is apparently one of these I can access at address 0x50 foft
FO 08:26 PM Feature #7: Implement I2C vga/hdmi support: Attached mux/level converter chip data sheet foft
FO 08:27 PM Feature #8: Implement 4 channel ADC: Attached ADC data sheet foft

FO 10:08 PM Feature #8 (In Progress): Implement 4 channel ADC: Written initial support based on data sheet and simulated. Not yet built into test core or tried on real hardware.
So far all four channels sampled, but only SIO input connected to core. foft

FO 09:25 PM Feature #13: 32x speed cpu without wait states: Nope, this is not going to be so simple... Massive timing violations. foft

FO 10:15 PM Feature #14: Svideo core for first prototype: Debugged in isim to get lots of overflow/underflow/blanking/burst incorrect cases!
Added colour bars and asserts for under/overflow. Looks like we have more space than I thought to allow slightly higher luma scaling (224/256). Verifying... foft
FO 06:40 AM Feature #14: Svideo core for first prototype: Scaled luma with 64 space for chroma - when in composite mode only. No point throwing away svideo brightness.
Added composite to video selection menu - since the G pin is used for both it can't be generated together.
Built for v1 a... foft

FO 08:54 PM Feature #14: Svideo core for first prototype: Setting this up in the simulator so I can understand chroma better.
The problem seems to be that I've used all the space for luma and chroma is a sine wave +-255. For some reason it only allows space of 32 though - which is odd! Anywa... foft
FO 08:51 PM Feature #13: 32x speed cpu without wait states: I have something working on the simulator - alone. Now need to plug it into the core proper to see if it works. Will probably need some clever timequest rules too, since the read/write deadlines are different now. foft

FO 10:14 PM Feature #14: Svideo core for first prototype: Should add that this should not be done for direct chroma output for svideo... Since that is still on a 0-0.7V DAC output. foft
FO 10:14 PM Feature #14: Svideo core for first prototype: Panos tried out a new core with composite only - on green using the sync pin. Looks brighter but just black and white - on several TVS.
I think its black and white because...
Basically I re-scaled Y to use the full DAC range. Compo... foft
FO 07:58 PM Feature #14 (Closed): Svideo core for first prototype: Waiting the Chinese sun to rising, I decide to proceed with the "video mod" of our v 1.0 board. So I desolder the "vsync" pin 12 of video dac, and solder it again using a "kynar cable" to a near via, which drive directly to F15 of FPGA.
... foft

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