Activity

From 04/17/2017 to 05/16/2017

09:24 PM Feature #13: 32x speed cpu without wait states: I enabled 32x mode in the core and sorted out single cycle writes from the block ram for now. Hardly any difference i... foft
09:22 PM Bug #17: NTSC crashing on some builds: Ijor recommended I try registering the input directly from SDRAM. I've done this and see if it helps.
He is also k... foft

09:52 PM Bug #17 (Closed): NTSC crashing on some builds: Investigate why... On the v1 core this occurred when running the PLL at very high fVCO. However we already fixed that... foft
07:48 PM Bug #16 (Closed): Audio bug report for Altirra: One for the coders, please can you check if these bugs are present?
From post on atariage...
http://atariage.com/... foft

09:42 PM Feature #15: Implement programmable PLL: Attaching PLL chip datasheet foft
09:41 PM Feature #15 (New): Implement programmable PLL: See if the programmable PLL works. This will allow us to support different/custom VGA modes, once we have EDID/DDC wo... foft
08:38 PM Feature #13: 32x speed cpu without wait states: So thinking about options...
Double the main clock speed and pipeline a bit
or
Output next address from antic a... foft
08:34 PM Feature #7: Implement I2C vga/hdmi support: Used this controller for the ADC on v1: https://eewiki.net/pages/viewpage.action?pageId=10125324
So I guess I just n... foft
08:30 PM Feature #7: Implement I2C vga/hdmi support: DDC looks a little funkier foft
08:28 PM Feature #7: Implement I2C vga/hdmi support: EDID is apparently one of these I can access at address 0x50 foft
08:26 PM Feature #7: Implement I2C vga/hdmi support: Attached mux/level converter chip data sheet foft
08:27 PM Feature #8: Implement 4 channel ADC: Attached ADC data sheet foft

10:08 PM Feature #8 (In Progress): Implement 4 channel ADC: Written initial support based on data sheet and simulated. Not yet built into test core or tried on real hardware.
... foft

09:25 PM Feature #13: 32x speed cpu without wait states: Nope, this is not going to be so simple... Massive timing violations. foft

10:15 PM Feature #14: Svideo core for first prototype: Debugged in isim to get lots of overflow/underflow/blanking/burst incorrect cases!
Added colour bars and asserts for... foft
06:40 AM Feature #14: Svideo core for first prototype: Scaled luma with 64 space for chroma - when in composite mode only. No point throwing away svideo brightness.
Adde... foft

08:54 PM Feature #14: Svideo core for first prototype: Setting this up in the simulator so I can understand chroma better.
The problem seems to be that I've used all the... foft
08:51 PM Feature #13: 32x speed cpu without wait states: I have something working on the simulator - alone. Now need to plug it into the core proper to see if it works. Will ... foft

10:14 PM Feature #14: Svideo core for first prototype: Should add that this should not be done for direct chroma output for svideo... Since that is still on a 0-0.7V DAC ou... foft
10:14 PM Feature #14: Svideo core for first prototype: Panos tried out a new core with composite only - on green using the sync pin. Looks brighter but just black and white... foft
07:58 PM Feature #14 (Closed): Svideo core for first prototype: Waiting the Chinese sun to rising, I decide to proceed with the "video mod" of our v 1.0 board. So I desolder the "vs... foft

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