Activity
From 04/19/2017 to 05/18/2017
05/18/2017
- FO 11:01 PM Feature #8: Implement 4 channel ADC
- Sigh, it definitely works but if I read say channel 1 - I still receive input from the other channels
- FO 09:00 PM Feature #8: Implement 4 channel ADC
- Debugged and now working.
PBI and SIO audio will be mixed. For now I'm not feeding MIC_L and MIC_R anywhere - these will be connected to some sampler register. I guess D500 and D501 if the 'replay cartrige mode' is enabled. - FO 06:56 AM Feature #8: Implement 4 channel ADC
- Now I have the board its clear this needs debugging.
- FO 06:58 AM Feature #1: Svideo sync line support
- Received the board and gave this a go. svideo and composite look nice and bright now. However saturation is too low, need to work out how to boost this without too much impact to brightness.
Also need to work out why its just black an...
05/16/2017
- FO 09:24 PM Feature #13: 32x speed cpu without wait states
- I enabled 32x mode in the core and sorted out single cycle writes from the block ram for now. Hardly any difference in sysinfo but good to see at least some difference.
- FO 09:22 PM Bug #17: NTSC crashing on some builds
- Ijor recommended I try registering the input directly from SDRAM. I've done this and see if it helps.
He is also kindly helping me write some correct timequest rules, really appreciated:) - FO 08:30 PM It is time!
- Panos will be in touch about shipping...
05/12/2017
- FO 09:52 PM Bug #17 (Closed): NTSC crashing on some builds
- Investigate why... On the v1 core this occurred when running the PLL at very high fVCO. However we already fixed that in v1, so not sure why.
- FO 07:48 PM Bug #16 (Closed): Audio bug report for Altirra
- One for the coders, please can you check if these bugs are present?
From post on atariage...
http://atariage.com/forums/topic/256683-altirra-280-released/page-24#entry3760704
Let me report a couple of issues with POKEY chip in Altir...
05/11/2017
- FO 09:42 PM Feature #15: Implement programmable PLL
- Attaching PLL chip datasheet
- FO 09:41 PM Feature #15 (New): Implement programmable PLL
- See if the programmable PLL works. This will allow us to support different/custom VGA modes, once we have EDID/DDC working. For now I just want to find out if its alive.
- FO 08:38 PM Feature #13: 32x speed cpu without wait states
- So thinking about options...
Double the main clock speed and pipeline a bit
or
Output next address from antic and the cpu, so I can read the memory 1 cycle earlier - antic clearly knows what it will read, does the 6502 core?
or
A... - FO 08:34 PM Feature #7: Implement I2C vga/hdmi support
- Used this controller for the ADC on v1: https://eewiki.net/pages/viewpage.action?pageId=10125324
So I guess I just need to wire this to the ZPU, then I can experiment with this in firmware.
I guess a write FIFO that captures 16 bits ... - FO 08:30 PM Feature #7: Implement I2C vga/hdmi support
- DDC looks a little funkier
- FO 08:28 PM Feature #7: Implement I2C vga/hdmi support
- EDID is apparently one of these I can access at address 0x50
- FO 08:26 PM Feature #7: Implement I2C vga/hdmi support
- Attached mux/level converter chip data sheet
- FO 08:27 PM Feature #8: Implement 4 channel ADC
- Attached ADC data sheet
- FO 08:25 PM No sign of FT232 chips
- Panos is chasing up - and if not good news he will order from somewhere quicker!
In the meantime I've added ADC support to the new core, important for SIO sounds such as tapes with speech and just plain interference from the cable!
05/08/2017
- FO 10:08 PM Feature #8 (In Progress): Implement 4 channel ADC
- Written initial support based on data sheet and simulated. Not yet built into test core or tried on real hardware.
So far all four channels sampled, but only SIO input connected to core.
05/04/2017
- FO 09:25 PM Feature #13: 32x speed cpu without wait states
- Nope, this is not going to be so simple... Massive timing violations.
05/03/2017
- FO 08:27 PM Missing parts
- Panos is waiting for the last few remaining parts to arrive. Most notably the FT232 USB chip. We're expecting they will arrive later this week.
05/02/2017
- FO 10:15 PM Feature #14: Svideo core for first prototype
- Debugged in isim to get lots of overflow/underflow/blanking/burst incorrect cases!
Added colour bars and asserts for under/overflow. Looks like we have more space than I thought to allow slightly higher luma scaling (224/256). Verifying... - FO 06:40 AM Feature #14: Svideo core for first prototype
- Scaled luma with 64 space for chroma - when in composite mode only. No point throwing away svideo brightness.
Added composite to video selection menu - since the G pin is used for both it can't be generated together.
Built for v1 a... - FO 06:38 AM Sub PCB - now populated!
- !sub-board-pop.jpg!
04/30/2017
- FO 09:06 PM Sub-board
- Here is the first picture of a sub-board, which also arrived in Greece. None completed yet but all the parts fit - and they fit in the Mhero S R case.
!sub-board.jpg!
- FO 09:01 PM Video DAC regulator patch
- Here is a picture of the patch Panos has skillfully applied to the boards.
!patch.jpg! - FO 08:58 PM Boards received
- The boards arrived in Greece. Panos is in the process of adding some final parts and trying them out.
Some good news:
FPGA is seen on JTAG
FPGA can be flashed ok
The core runs, the USB keyboard is working, SD card access is workin...
04/26/2017
- SA 11:43 PM Document: Eclaire XL v1.0 Board Spec
- Eclaire XL v1.0 Board Spec
- FO 08:54 PM Feature #14: Svideo core for first prototype
- Setting this up in the simulator so I can understand chroma better.
The problem seems to be that I've used all the space for luma and chroma is a sine wave +-255. For some reason it only allows space of 32 though - which is odd! Anywa... - FO 08:51 PM Feature #13: 32x speed cpu without wait states
- I have something working on the simulator - alone. Now need to plug it into the core proper to see if it works. Will probably need some clever timequest rules too, since the read/write deadlines are different now.
04/24/2017
- FO 10:14 PM Feature #14: Svideo core for first prototype
- Should add that this should not be done for direct chroma output for svideo... Since that is still on a 0-0.7V DAC output.
- FO 10:14 PM Feature #14: Svideo core for first prototype
- Panos tried out a new core with composite only - on green using the sync pin. Looks brighter but just black and white - on several TVS.
I think its black and white because...
Basically I re-scaled Y to use the full DAC range. Compo... - FO 07:58 PM Feature #14 (Closed): Svideo core for first prototype
- Waiting the Chinese sun to rising, I decide to proceed with the "video mod" of our v 1.0 board. So I desolder the "vsync" pin 12 of video dac, and solder it again using a "kynar cable" to a near via, which drive directly to F15 of FPGA.
... - FO 07:56 PM Pictures!
- The PCB company sent us an initial picture!
!v3board_small.jpg!