EclaireXL

05/27/2017

10:49 PM Feature #2: PBI support

Still no luck with signaltap, so got the real logic analyzer on the GPIOs to debug. Squashed one sync bug but still n... foft

10:28 AM Feature #2: PBI support

I started to bisect to find the problem - and found the core stops working when connecting RAS and CAS! Which are lar... foft

10:46 AM Bug #17: NTSC crashing on some builds

Interesting when I build on AWS I get completely screwed up builds with the registered sdram input. Seemingly every t... foft

05/26/2017

08:53 PM Feature #2: PBI support

The core blows up with signaltap2 enabled! Looks great on sim, but I can't see what is going wrong on the actual hard... foft

05/25/2017

11:29 PM Feature #2: PBI support

foft wrote:
> Made several more fixes and the core no longer crashes with PBI enabled. However it all crashes when I... sadosp

11:10 PM Feature #2: PBI support

Made several more fixes and the core no longer crashes with PBI enabled. However it all crashes when I plug in a cart... foft

05/24/2017

10:09 PM Feature #2: PBI support

Looking good on simulation now but does not run on the board. I think the issue is when pbi takes over the bus when a... foft

05/23/2017

09:43 PM Feature #2: PBI support

Integrated into the description and synthesising:-)
For now I took the strategy of delaying the cycle until we kno... foft

05/22/2017

09:55 PM Feature #2: PBI support

PBI looking good on simulation (bit itself). Based timings on the Freddie data sheet.
Made a start on wiring it up t... foft

05/21/2017

02:37 PM Feature #2: PBI support

Started on a PBI component that will correctly communicate with the bus. Then this can be checked/simulated - and as ... foft

05/20/2017

10:39 PM Bug #17: NTSC crashing on some builds

I've still had bad builds since registering the sdram input directly.
I tried to specify an externally switchable ... foft

10:36 PM Feature #8: Implement 4 channel ADC

So I guess we should have some more passive components here. On the other hand I'm kind of attached to SIO noise down... foft

10:35 PM Feature #8: Implement 4 channel ADC

Pretty sure this is down to floating inputs. Since there is no driver and low capacitance the input picks up the prev... foft

05/18/2017

11:01 PM Feature #8: Implement 4 channel ADC

Sigh, it definitely works but if I read say channel 1 - I still receive input from the other channels foft

09:00 PM Feature #8: Implement 4 channel ADC

Debugged and now working.
PBI and SIO audio will be mixed. For now I'm not feeding MIC_L and MIC_R anywhere - thes... foft

06:56 AM Feature #8: Implement 4 channel ADC

Now I have the board its clear this needs debugging. foft

06:58 AM Feature #1: Svideo sync line support

Received the board and gave this a go. svideo and composite look nice and bright now. However saturation is too low, ... foft

05/16/2017

09:24 PM Feature #13: 32x speed cpu without wait states

I enabled 32x mode in the core and sorted out single cycle writes from the block ram for now. Hardly any difference i... foft

09:22 PM Bug #17: NTSC crashing on some builds

Ijor recommended I try registering the input directly from SDRAM. I've done this and see if it helps.
He is also k... foft

05/12/2017

09:52 PM Bug #17 (Closed): NTSC crashing on some builds

Investigate why... On the v1 core this occurred when running the PLL at very high fVCO. However we already fixed that... foft

07:48 PM Bug #16 (Closed): Audio bug report for Altirra

One for the coders, please can you check if these bugs are present?
From post on atariage...
http://atariage.com/... foft

05/11/2017

09:42 PM Feature #15: Implement programmable PLL

Attaching PLL chip datasheet foft

09:41 PM Feature #15 (New): Implement programmable PLL

See if the programmable PLL works. This will allow us to support different/custom VGA modes, once we have EDID/DDC wo... foft

08:38 PM Feature #13: 32x speed cpu without wait states

So thinking about options...
Double the main clock speed and pipeline a bit
or
Output next address from antic a... foft

08:34 PM Feature #7: Implement I2C vga/hdmi support

Used this controller for the ADC on v1: https://eewiki.net/pages/viewpage.action?pageId=10125324
So I guess I just n... foft

08:30 PM Feature #7: Implement I2C vga/hdmi support

DDC looks a little funkier foft

08:28 PM Feature #7: Implement I2C vga/hdmi support

EDID is apparently one of these I can access at address 0x50 foft

08:26 PM Feature #7: Implement I2C vga/hdmi support

Attached mux/level converter chip data sheet foft

08:27 PM Feature #8: Implement 4 channel ADC

Attached ADC data sheet foft

05/08/2017

10:08 PM Feature #8 (In Progress): Implement 4 channel ADC

Written initial support based on data sheet and simulated. Not yet built into test core or tried on real hardware.
... foft

05/04/2017

09:25 PM Feature #13: 32x speed cpu without wait states

Nope, this is not going to be so simple... Massive timing violations. foft

05/02/2017

10:15 PM Feature #14: Svideo core for first prototype

Debugged in isim to get lots of overflow/underflow/blanking/burst incorrect cases!
Added colour bars and asserts for... foft

06:40 AM Feature #14: Svideo core for first prototype

Scaled luma with 64 space for chroma - when in composite mode only. No point throwing away svideo brightness.
Adde... foft