Pinouts » History » Version 10
foft, 04/15/2018 08:05 PM
| 1 | 1 | foft | h1. Pinouts |
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| 2 | 3 | foft | |
| 3 | 2 | foft | h2. V1 |
| 4 | 3 | foft | |
| 5 | 9 | foft | h3. Use in core |
| 6 | |||
| 7 | *Cartridge/PBI interface* |
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| 8 | 10 | foft | 1: CCTL_N |
| 9 | 2: PHI2 |
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| 10 | 3: RD5 |
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| 11 | 4: RW_N |
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| 12 | 5: A10 |
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| 13 | 6: A11 |
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| 14 | 7: S5_N |
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| 15 | 8: D7 |
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| 16 | 9: D6 |
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| 17 | 10:D3 |
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| 18 | 11:NC |
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| 19 | 12:NC |
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| 20 | 13:D0 |
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| 21 | 14:A12 |
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| 22 | 15:D1 |
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| 23 | 16:A9 |
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| 24 | 17:D2 |
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| 25 | 18:A8 |
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| 26 | 19:D5 |
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| 27 | 20:A7 |
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| 28 | 21:D4 |
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| 29 | 22:A6 |
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| 30 | 23:A0 |
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| 31 | 24:A5 |
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| 32 | 25:A1 |
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| 33 | 26:A4 |
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| 34 | 27:A2 |
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| 35 | 28:A3 |
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| 36 | 29:MIC_PBI (To ADC jumper) |
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| 37 | 30:MIC_PBI (To ADC jumper) |
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| 38 | 31:RD4 |
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| 39 | 32:S4_N |
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| 40 | 33:EXTSEL_N |
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| 41 | 34:A13 |
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| 42 | 35:A14 |
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| 43 | 36:A15 |
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| 44 | 37:MPD_N |
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| 45 | 38:REF_N |
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| 46 | 39:IRQ_N |
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| 47 | 40:RST_N |
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| 48 | 9 | foft | |
| 49 | 10 | foft | *SIO interface* |
| 50 | 1: SIO CLOCK OUT |
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| 51 | 2: SIO COMMAND |
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| 52 | 3: SIO IN |
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| 53 | 4: SIO PROCEED |
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| 54 | 5: SIO IRQ |
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| 55 | 6: SIO CLOCK IN |
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| 56 | 7: SIO OUT |
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| 57 | 8: SIO MOTOR EN |
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| 58 | 9: SIO MIC (To ADC jumper) |
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| 59 | 10:SIO MOTOR EN |
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| 60 | 9 | foft | |
| 61 | h3. By connection to FPGA |
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| 62 | 1 | foft | |
| 63 | 10 | foft | Useful information if building your own core. |
| 64 | In general pins have 100 ohm resistance to the FPGA itself. The FPGA max voltage on IO is 3.3V. |
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| 65 | |||
| 66 | *GPIO:* |
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| 67 | 1-10: Direct to FPGA |
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| 68 | 11: 5V |
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| 69 | 12: GND |
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| 70 | 13-28: Direct to FPGA |
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| 71 | 29: 3.3V |
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| 72 | 30: GND |
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| 73 | 31-40: Direct to FPGA |
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| 74 | |||
| 75 | *Cartridge/PBI interface* |
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| 76 | All level shifted to 3.3V. |
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| 77 | Special pins: |
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| 78 | 31:10k pulldown |
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| 79 | 3: 10k pulldown |
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| 80 | 10/11: NC |
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| 81 | 29:To ADC jumper (PBI) |
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| 82 | 30:To ADC jumper (PBI) |
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| 83 | 33:4.7k pullup to 5V |
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| 84 | 37:4.7k pullup to 5V |
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| 85 | 38:4.7k pullup to 5V |
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| 86 | 39:4.7k pullup to 5V |
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| 87 | |||
| 88 | *SIO interface* |
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| 89 | 1-7: 3.3V level shifted, 5V pull-up. |
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| 90 | 8,10: 5V transistor drive (for tape motor) |
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| 91 | 9: To ADC jumper (SIO) |
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| 92 | |||
| 93 | 2 | foft | h2. V2 |
| 94 | 6 | foft | |
| 95 | h3. Use in core |
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| 96 | |||
| 97 | *Interface 1:* |
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| 98 | 1-16: A0-A15 (1=A0,2=A1, etc) |
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| 99 | 17-24: D0-D7 (17=D0, 18=D1 etc) |
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| 100 | 25: PHI2 |
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| 101 | 26: HALT (not implemented yet) |
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| 102 | 27: RST_N |
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| 103 | 28: IRQ_N |
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| 104 | 29: D1XX (not implemented yet) |
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| 105 | 30: CASINH_N |
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| 106 | 31: CCTL_N |
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| 107 | 32: REF_N |
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| 108 | 33: CAS_N |
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| 109 | 7 | foft | 34: MPD_N |
| 110 | 35: RAS_N |
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| 111 | 36: RW_N |
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| 112 | 37: RD4 |
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| 113 | 38: S4_N |
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| 114 | 39: S5_N |
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| 115 | 40: RD5 |
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| 116 | |||
| 117 | *Interface 2:* |
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| 118 | 1: USBDM (FTDI USB RS232) |
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| 119 | 2: USBRES (FTDI USB RS232) |
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| 120 | 3: USBDP (FTDI USB RS232) |
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| 121 | 4: GND |
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| 122 | 5: 5V0 |
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| 123 | 6: 5V0 |
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| 124 | 7: J2 ANAL_B (Paddle in) |
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| 125 | 8: J2 ANAL_A |
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| 126 | 9: J1 ANAL_B |
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| 127 | 10:J1 ANAL_A |
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| 128 | 11:J2 FIRE |
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| 129 | 12:J2 UP |
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| 130 | 13:J2 DOWN |
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| 131 | 14:J2 LEFT |
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| 132 | 15:J2 RIGHT |
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| 133 | 16:J1 FIRE |
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| 134 | 17:J1 UP |
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| 135 | 18:J1 DOWN |
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| 136 | 19:J1 LEFT |
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| 137 | 20:J1 RIGHT |
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| 138 | 21:J4 FIRE |
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| 139 | 22:J4 UP |
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| 140 | 23:J4 DOWN |
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| 141 | 24:J4 LEFT |
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| 142 | 25:J4 RIGHT |
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| 143 | 26:J3 FIRE |
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| 144 | 27:J3 UP |
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| 145 | 28:J3 DOWN |
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| 146 | 29:J3 LEFT |
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| 147 | 30:J3 RIGHT |
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| 148 | 31:GND |
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| 149 | 6 | foft | 32:SIO IRQ |
| 150 | 1 | foft | 33:SIO PROCEED |
| 151 | 8 | foft | 34:SIO MOTOR_EN |
| 152 | 35:SIO COMMAND |
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| 153 | 36:SIO DATA OUT |
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| 154 | 1 | foft | 37:SIO DATA IN |
| 155 | 38:CLOCK OUT |
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| 156 | 39:CLOCK IN |
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| 157 | 6 | foft | 40:EXTSEL_N |
| 158 | |||
| 159 | 1 | foft | h3. By connection to FPGA |
| 160 | |||
| 161 | Useful information if building your own core. |
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| 162 | 5 | foft | In general pins have 100 ohm resistance to the FPGA itself. The FPGA max voltage on IO is 3.3V. |
| 163 | 1 | foft | |
| 164 | *GPIO:* |
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| 165 | 1-17: direct to FPGA |
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| 166 | 18: SDA (i2c) - clock gen also on here (*V2 FIX only*) |
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| 167 | 19: SCL (i2c) - clock gen also on here (*V2 FIX only*) |
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| 168 | 20-22: GND |
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| 169 | 23-34: 3.3V |
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| 170 | 25-26: 5.0V |
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| 171 | |||
| 172 | *Interface 1:* |
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| 173 | All level shifted to 3.3V. |
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| 174 | Special pins: |
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| 175 | 10 | foft | 37:10k pulldown |
| 176 | 40:10k pulldown |
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| 177 | 34:4.7k pullup to 5V |
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| 178 | 28:4.7k pullup to 5V |
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| 179 | 32:2k pullup to 5V (*V2 FIX 2k, V2 4.7k*) |
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| 180 | 1 | foft | |
| 181 | *Interface 2:* |
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| 182 | 1-3: USB to FTDI |
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| 183 | 4: GND |
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| 184 | 5,6: 5V |
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| 185 | 10 | foft | 7-10: Charge cap, FPGA compares with ref voltage (about 2V) |
| 186 | 11-30: level shifted to 3.3V. 4.7k pullup to 5V. Direction pins have extra 220 ohm resistance in addition (330 ohm total to FPGA). |
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| 187 | 1 | foft | 31: GND |
| 188 | 32-33: level shifted to 3.3V. 4.7k pullup to 5V |
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| 189 | 34: 5V transistor drive (for tape motor) |
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| 190 | 10 | foft | 35-40: level shifted to 3.3V. 4.7k pullup to 5V |