Pinouts » History » Version 7
foft, 04/15/2018 07:35 PM
| 1 | 1 | foft | h1. Pinouts |
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| 2 | 3 | foft | |
| 3 | 2 | foft | h2. V1 |
| 4 | 3 | foft | |
| 5 | 2 | foft | h2. V2 |
| 6 | 3 | foft | |
| 7 | 1 | foft | h3. Use in core |
| 8 | |||
| 9 | 6 | foft | Interface 1: |
| 10 | 1-16: A0-A15 (1=A0,2=A1, etc) |
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| 11 | 17-24: D0-D7 (17=D0, 18=D1 etc) |
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| 12 | 25: PHI2 |
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| 13 | 26: HALT (not implemented yet) |
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| 14 | 27: RST_N |
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| 15 | 28: IRQ_N |
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| 16 | 29: D1XX (not implemented yet) |
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| 17 | 30: CASINH_N |
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| 18 | 31: CCTL_N |
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| 19 | 32: REF_N |
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| 20 | 33: CAS_N |
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| 21 | 34: MPD_N |
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| 22 | 35: RAS_N |
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| 23 | 36: RW_N |
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| 24 | 37: RD4 |
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| 25 | 38: S4_N |
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| 26 | 39: S5_N |
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| 27 | 40: RD5 |
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| 28 | |||
| 29 | *Interface 2:* |
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| 30 | 7 | foft | 1: USBDM (FTDI USB RS232) |
| 31 | 2: USBRES (FTDI USB RS232) |
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| 32 | 3: USBDP (FTDI USB RS232) |
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| 33 | 4: GND |
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| 34 | 5: 5V0 |
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| 35 | 6: 5V0 |
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| 36 | 7: J2 ANAL_B (Paddle in) |
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| 37 | 8: J2 ANAL_A |
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| 38 | 9: J1 ANAL_B |
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| 39 | 10:J1 ANAL_A |
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| 40 | 11:J2 FIRE |
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| 41 | 12:J2 UP |
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| 42 | 13:J2 DOWN |
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| 43 | 14:J2 LEFT |
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| 44 | 15:J2 RIGHT |
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| 45 | 16:J1 FIRE |
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| 46 | 17:J1 UP |
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| 47 | 18:J1 DOWN |
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| 48 | 19:J1 LEFT |
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| 49 | 20:J1 RIGHT |
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| 50 | 21:J4 FIRE |
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| 51 | 22:J4 UP |
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| 52 | 23:J4 DOWN |
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| 53 | 24:J4 LEFT |
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| 54 | 25:J4 RIGHT |
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| 55 | 26:J3 FIRE |
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| 56 | 27:J3 UP |
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| 57 | 28:J3 DOWN |
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| 58 | 29:J3 LEFT |
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| 59 | 30:J3 RIGHT |
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| 60 | 31:GND |
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| 61 | 32:SIO IRQ |
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| 62 | 33:SIO PROCEED |
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| 63 | 34:SIO MOTOR_EN |
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| 64 | 35:SIO COMMAND |
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| 65 | 36:SIO DATA OUT |
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| 66 | 37:SIO DATA IN |
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| 67 | 38:CLOCK OUT |
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| 68 | 39:CLOCK IN |
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| 69 | 40:EXTSEL_N |
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| 70 | 6 | foft | |
| 71 | 5 | foft | h3. By connection to FPGA |
| 72 | 1 | foft | |
| 73 | *GPIO:* |
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| 74 | 1-17: direct to FPGA |
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| 75 | 6 | foft | 18: SDA (i2c) - clock gen also on here (*V2 FIX only*) |
| 76 | 19: SCL (i2c) - clock gen also on here (*V2 FIX only*) |
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| 77 | 1 | foft | 20-22: GND |
| 78 | 23-34: 3.3V |
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| 79 | 25-26: 5.0V |
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| 80 | |||
| 81 | 5 | foft | *Interface 1:* |
| 82 | 1 | foft | All level shifted to 3.3V. |
| 83 | Special pins: |
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| 84 | 37:RD4: 10k pulldown |
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| 85 | 40:RD5: 10k pulldown |
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| 86 | 34:MPD_N: 4.7k pullup to 5V |
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| 87 | 28:IRQ_N: 4.7k pullup to 5V |
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| 88 | 32:REF_N: 2k pullup to 5V |
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| 89 | |||
| 90 | 5 | foft | *Interface 2:* |
| 91 | 1 | foft | 1-3: USB to FTDI |
| 92 | 4: GND |
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| 93 | 5,6: 5V |
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| 94 | 7-10: Charge cap, FPGA compares with ref voltage |
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| 95 | 11-30: level shifted to 3.3V. 4.7k pullup to 5V. Direction pins have extra 220 ohm resistance (needed?) |
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| 96 | 31: GND |
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| 97 | 32-33: level shifted to 3.3V. 4.7k pullup to 5V |
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| 98 | 34: 5V transistor drive (for tape motor) |
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| 99 | 35-49: level shifted to 3.3V. 4.7k pullup o 5V |
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| 100 | 40: EXTSEL_N: level shifted to 3.3V. 4.7k pullup to 5V |