Pinouts » History » Version 9
foft, 04/15/2018 07:48 PM
| 1 | 1 | foft | h1. Pinouts |
|---|---|---|---|
| 2 | 3 | foft | |
| 3 | 2 | foft | h2. V1 |
| 4 | 3 | foft | |
| 5 | 9 | foft | h3. Use in core |
| 6 | |||
| 7 | *Cartridge/PBI interface* |
||
| 8 | |||
| 9 | |||
| 10 | |||
| 11 | h3. By connection to FPGA |
||
| 12 | |||
| 13 | 2 | foft | h2. V2 |
| 14 | 3 | foft | |
| 15 | 1 | foft | h3. Use in core |
| 16 | |||
| 17 | 8 | foft | *Interface 1:* |
| 18 | 6 | foft | 1-16: A0-A15 (1=A0,2=A1, etc) |
| 19 | 17-24: D0-D7 (17=D0, 18=D1 etc) |
||
| 20 | 25: PHI2 |
||
| 21 | 26: HALT (not implemented yet) |
||
| 22 | 27: RST_N |
||
| 23 | 28: IRQ_N |
||
| 24 | 29: D1XX (not implemented yet) |
||
| 25 | 30: CASINH_N |
||
| 26 | 31: CCTL_N |
||
| 27 | 32: REF_N |
||
| 28 | 33: CAS_N |
||
| 29 | 34: MPD_N |
||
| 30 | 35: RAS_N |
||
| 31 | 36: RW_N |
||
| 32 | 37: RD4 |
||
| 33 | 38: S4_N |
||
| 34 | 39: S5_N |
||
| 35 | 40: RD5 |
||
| 36 | |||
| 37 | *Interface 2:* |
||
| 38 | 7 | foft | 1: USBDM (FTDI USB RS232) |
| 39 | 2: USBRES (FTDI USB RS232) |
||
| 40 | 3: USBDP (FTDI USB RS232) |
||
| 41 | 4: GND |
||
| 42 | 5: 5V0 |
||
| 43 | 6: 5V0 |
||
| 44 | 7: J2 ANAL_B (Paddle in) |
||
| 45 | 8: J2 ANAL_A |
||
| 46 | 9: J1 ANAL_B |
||
| 47 | 10:J1 ANAL_A |
||
| 48 | 11:J2 FIRE |
||
| 49 | 12:J2 UP |
||
| 50 | 13:J2 DOWN |
||
| 51 | 14:J2 LEFT |
||
| 52 | 15:J2 RIGHT |
||
| 53 | 16:J1 FIRE |
||
| 54 | 17:J1 UP |
||
| 55 | 18:J1 DOWN |
||
| 56 | 19:J1 LEFT |
||
| 57 | 20:J1 RIGHT |
||
| 58 | 21:J4 FIRE |
||
| 59 | 22:J4 UP |
||
| 60 | 23:J4 DOWN |
||
| 61 | 24:J4 LEFT |
||
| 62 | 25:J4 RIGHT |
||
| 63 | 26:J3 FIRE |
||
| 64 | 27:J3 UP |
||
| 65 | 28:J3 DOWN |
||
| 66 | 29:J3 LEFT |
||
| 67 | 30:J3 RIGHT |
||
| 68 | 31:GND |
||
| 69 | 32:SIO IRQ |
||
| 70 | 33:SIO PROCEED |
||
| 71 | 34:SIO MOTOR_EN |
||
| 72 | 35:SIO COMMAND |
||
| 73 | 36:SIO DATA OUT |
||
| 74 | 37:SIO DATA IN |
||
| 75 | 38:CLOCK OUT |
||
| 76 | 39:CLOCK IN |
||
| 77 | 40:EXTSEL_N |
||
| 78 | 6 | foft | |
| 79 | 1 | foft | h3. By connection to FPGA |
| 80 | 8 | foft | |
| 81 | Useful information if building your own core. |
||
| 82 | In general pins have 100 ohm resistance to the FPGA itself. The FPGA max voltage on IO is 3.3V. |
||
| 83 | 1 | foft | |
| 84 | *GPIO:* |
||
| 85 | 1-17: direct to FPGA |
||
| 86 | 6 | foft | 18: SDA (i2c) - clock gen also on here (*V2 FIX only*) |
| 87 | 19: SCL (i2c) - clock gen also on here (*V2 FIX only*) |
||
| 88 | 1 | foft | 20-22: GND |
| 89 | 23-34: 3.3V |
||
| 90 | 25-26: 5.0V |
||
| 91 | 5 | foft | |
| 92 | 1 | foft | *Interface 1:* |
| 93 | All level shifted to 3.3V. |
||
| 94 | Special pins: |
||
| 95 | 37:RD4: 10k pulldown |
||
| 96 | 40:RD5: 10k pulldown |
||
| 97 | 34:MPD_N: 4.7k pullup to 5V |
||
| 98 | 28:IRQ_N: 4.7k pullup to 5V |
||
| 99 | 9 | foft | 32:REF_N: 2k pullup to 5V (*V2 FIX 2k, V2 4.7k*) |
| 100 | 1 | foft | |
| 101 | 5 | foft | *Interface 2:* |
| 102 | 1 | foft | 1-3: USB to FTDI |
| 103 | 4: GND |
||
| 104 | 5,6: 5V |
||
| 105 | 7-10: Charge cap, FPGA compares with ref voltage |
||
| 106 | 11-30: level shifted to 3.3V. 4.7k pullup to 5V. Direction pins have extra 220 ohm resistance (needed?) |
||
| 107 | 31: GND |
||
| 108 | 32-33: level shifted to 3.3V. 4.7k pullup to 5V |
||
| 109 | 34: 5V transistor drive (for tape motor) |
||
| 110 | 35-49: level shifted to 3.3V. 4.7k pullup o 5V |
||
| 111 | 40: EXTSEL_N: level shifted to 3.3V. 4.7k pullup to 5V |