Added by foft over 7 years ago. Updated almost 7 years ago.
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Description
See if the programmable PLL works. This will allow us to support different/custom VGA modes, once we have EDID/DDC working. For now I just want to find out if its alive.
Files
| Si5351-B.pdf (1.74 MB) Si5351-B.pdf | foft, 05/11/2017 09:42 PM | ||
| Si5351A-RevB-Registers.h (9.33 KB) Si5351A-RevB-Registers.h | foft, 02/04/2018 09:21 PM | ||
| AN619.pdf (1.83 MB) AN619.pdf | foft, 02/04/2018 09:22 PM |
Attached header file for programming clk0->10MHz and clk1->30MHz.
These are generated with clock builder pro, downloaded from ic vendor web site.
Going to power this up urgently before new boards made, to check hardware side is fine.
To do this I need to add i2c support to the ZPU. I'm out of ROM space without easy fixes. There is actually quite a lot space even on the EBA2, so adding 8K extra for now. Currently it was using bit 15 to decide rom/ram. I made it use 14 and 15 to choose ram. There is some hack I put in for the mist external sector buffer (it writes to ROM area!!) which might be broken by this.
Been adding i2c to the zpu. Mostly working I think, a few timing issues to solve.
OK, confirmed this chip is working. I programmed it over i2c and am now getting two different clocks output on CLK0 and CLK2 - 10MHz and 30MHz as I set up in the clk generator software.
Going to mark this back as normal priority since I now know the chip is connected ok and working.
foft wrote:
OK, confirmed this chip is working. I programmed it over i2c and am now getting two different clocks output on CLK0 and CLK2 - 10MHz and 30MHz as I set up in the clk generator software.
Going to mark this back as normal priority since I now know the chip is connected ok and working.
Congrats! ;-)